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1000 tulosta hakusanalla Chandra A Clements

Architectures ADPLL entièrement personnalisées à haute résolution et faible gigue

Architectures ADPLL entièrement personnalisées à haute résolution et faible gigue

Mohd Ziauddin Jahangir; P Chandra Shekar

Editions Notre Savoir
2025
pokkari
Toutes les PLL num riques sont consid r es comme un remplacement efficace en raison de la grande immunit des circuits num riques aux variations de PVT. Cependant, les ADPLL souffrent d'un probl me de faible r solution et de gigue/ bruit de phase lev , en plus des probl mes fondamentaux li s la complexit des proc dures de conception. Des tudes documentaires et des v rifications exp rimentales ont permis de constater que les ADPLL existantes doivent encore relever certains d fis li s la r solution, la gigue et au bruit de phase. De m me, il a t constat que les mod les utilis s pour d crire les ADPLL pr sentaient des lacunes. cet gard, une classification approfondie des architectures ADPLL existantes a t r alis e. Certaines des architectures trouv es dans la litt rature ont t examin es de mani re critique par une nouvelle conception et une v rification par simulation diff rents niveaux de la conception avec un large ventail d'outils de simulation/ mulation. Une analyse comparative a t effectu e et les lacunes de chaque architecture ont t identifi es de mani re critique. Des m thodes pour am liorer la r solution et le bruit de phase ont t propos es et v rifi es par simulation.
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Losing a Parent to Death in the Early Years

Losing a Parent to Death in the Early Years

Lieberman Alicia; Compton Nancy C.; Horn Patricia van; Ippen Chandra Ghosh

ZERO TO THREE: National Center for Infants, Toddlers, Families
2003
sidottu
Four therapists and psychiatrists at the San Francisco General Hospital's Child Trauma Research Project provide therapists with guidelines for treating infants and children who have experienced the death of a parent. Coverage includes common reactions, caregiver reactions, child responses, and the v
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Test Resource Partitioning for System-on-a-Chip

Test Resource Partitioning for System-on-a-Chip

Vikram Iyengar; Anshuman Chandra

Springer-Verlag New York Inc.
2002
sidottu
Test Resource Partitioning for System-on-a-Chip is about test resource partitioning and optimization techniques for plug-and-play system-on-a-chip (SOC) test automation. Plug-and-play refers to the paradigm in which core-to-core interfaces as well as core-to-SOC logic interfaces are standardized, such that cores can be easily plugged into "virtual sockets" on the SOC design, and core tests can be plugged into the SOC during test without substantial effort on the part of the system integrator. The goal of the book is to position test resource partitioning in the context of SOC test automation, as well as to generate interest and motivate research on this important topic. SOC integrated circuits composed of embedded cores are now commonplace. Nevertheless, There remain several roadblocks to rapid and efficient system integration. Test development is seen as a major bottleneck in SOC design, and test challenges are a major contributor to the widening gap between design capability and manufacturing capacity. Testing SOCs is especially challenging in the absence of standardized test structures, test automation tools, and test protocols. Test Resource Partitioning for System-on-a-Chip responds to a pressing need for a structured methodology for SOC test automation. It presents new techniques for the partitioning and optimization of the three major SOC test resources: test hardware, testing time and test data volume. Test Resource Partitioning for System-on-a-Chip paves the way for a powerful integrated framework to automate the test flow for a large number of cores in an SOC in a plug-and-play fashion. The framework presented allows the system integrator to reduce test cost and meet short time-to-market requirements.
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Test Resource Partitioning for System-on-a-Chip

Test Resource Partitioning for System-on-a-Chip

Vikram Iyengar; Anshuman Chandra

Springer-Verlag New York Inc.
2012
nidottu
Test Resource Partitioning for System-on-a-Chip is about test resource partitioning and optimization techniques for plug-and-play system-on-a-chip (SOC) test automation. Plug-and-play refers to the paradigm in which core-to-core interfaces as well as core-to-SOC logic interfaces are standardized, such that cores can be easily plugged into "virtual sockets" on the SOC design, and core tests can be plugged into the SOC during test without substantial effort on the part of the system integrator. The goal of the book is to position test resource partitioning in the context of SOC test automation, as well as to generate interest and motivate research on this important topic. SOC integrated circuits composed of embedded cores are now commonplace. Nevertheless, There remain several roadblocks to rapid and efficient system integration. Test development is seen as a major bottleneck in SOC design, and test challenges are a major contributor to the widening gap between design capability and manufacturing capacity. Testing SOCs is especially challenging in the absence of standardized test structures, test automation tools, and test protocols. Test Resource Partitioning for System-on-a-Chip responds to a pressing need for a structured methodology for SOC test automation. It presents new techniques for the partitioning and optimization of the three major SOC test resources: test hardware, testing time and test data volume. Test Resource Partitioning for System-on-a-Chip paves the way for a powerful integrated framework to automate the test flow for a large number of cores in an SOC in a plug-and-play fashion. The framework presented allows the system integrator to reduce test cost and meet short time-to-market requirements.
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Father of the capital city of Honorable C M Shri N. Chandra Babu Naidu

Father of the capital city of Honorable C M Shri N. Chandra Babu Naidu

A Ramababu; Morusu Siva Sankar; N Sreeramulu

Scholars' Press
2019
pokkari
Amaravati is the de facto capital city of the Indian state of Andhra Pradesh. The planned city is located on the southern banks of the Krishna river in Guntur district, within the Andhra Pradesh Capital Region, being built on a 217 sq km riverfront designed to have 51% of green spaces and 10% of water bodies. The word "Amaravati" derives from the historical Amaravathi Temple town, the ancient capital of the Satavahana dynasty. The foundation stone was laid on 22 October 2015, at Uddandarayunipalem area by the Prime Minister, Narendra Modi. The metropolitan area of Guntur and Vijayawada are the major conurbations of Amaravati. Amaravati is being constructed to serve as the new capital city of Andhra Pradesh, after Telangana was split off as a separate state in 2014. The former capital city, Hyderabad, is now located inside Telangana. A new capital city had to be either assigned or constructed on the remaining territory of Andhra Pradesh. The choice fell on the Amaravati, which was specifically designed to that end. For a transitional period of no more than 10 years, Hyderabad could continue to serve as the residence of Andhra Pradesh's official state institutions.
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Une approche durable pour la biorestauration des polluants à base de métaux lourds

Une approche durable pour la biorestauration des polluants à base de métaux lourds

Annika Durve-Gupta; Naresh Chandra

Editions Notre Savoir
2023
pokkari
Les polluants base de m taux lourds sont rejet s dans les rivi res, les sols et l'atmosph re, en raison du d veloppement de l'agro-industrie et de la m tallurgie, ainsi que des engrais et des pesticides. Ils ne sont pas biod gradables et peuvent s'accumuler dans les syst mes vivants, contaminant ainsi la cha ne alimentaire. Les solutions physiques et chimiques de nettoyage des m taux lourds sont co teuses et nuisibles l' cologie environnante. En raison de la capacit av r e des microbes, en particulier des bact ries, s questrer et convertir les polluants, la biorestauration microbienne s'est impos e comme une technique viable pour r duire les m taux lourds dans l'environnement. Les microbes ont d velopp plusieurs techniques de biorestauration. Ces processus se distinguent par leurs exigences et leurs avantages, et leur efficacit est d termin e par le type de microbe et de toxines en cause. Les microbes peuvent tre largement utilis s pour produire des nanoparticules en raison de leur facilit de manipulation et de traitement, de la n cessit d'un milieu faible co t, d'une mise l' chelle simple et d'une faisabilit conomique avec la capacit d'adsorber et de r duire les ions m talliques en nanoparticules par le biais de processus m taboliques. L'utilisation de ressources renouvelables pour la r duction des m taux et la biosynth se de nanoparticules constitue une technique propre, non toxique et durable.
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