Digital Computer Arithmetic Datapath Design Using Verilog HDL

Kirjan Digital Computer Arithmetic Datapath Design Using Verilog HDL (2012) on kirjoittanut James E. Stine. Kirjan kieli on englanti, ja sen on kustantanut Springer-Verlag New York Inc.. Kirja on laajuudeltaan 181 sivua ja se on nidottu.

The role of arithmetic in datapath design in VLSI design has been increasing in importance over the last several years due to the demand for processors that are smaller, faster, and dissipate less power. Unfortunately, this means that many of these datapaths will be complex both algorithmically and circuit­ wise. As the complexity of the chips increases, less importance will be placed on understanding how a particular arithmetic datapath design is implemented and more importance will be given to when a product will be placed on the market. This is because many tools that are available today, are automated to help the digital system designer maximize their efficiently. Unfortunately, this may lead to problems when implementing particular datapaths. The design of high-performance architectures is becoming more compli­ cated because the level of integration that is capable for many of these chips is in the billions. Many engineers rely heavily on software tools to optimize their work, therefore, as designs are getting more complex less understanding is going into a particular implementation because it can be generated automati­ cally. Although software tools are a highly valuable asset to designer, the value of these tools does not diminish the importance of understanding datapath ele­ ments. Therefore, a digital system designer should be aware of how algorithms can be implemented for datapath elements. Unfortunately, due to the complex­ ity of some of these algorithms, it is sometimes difficult to understand how a particular algorithm is implemented without seeing the actual code.