Kirjojen hintavertailu. Mukana 12 474 932 kirjaa ja 12 kauppaa.

Kirjailija

Francky Catthoor

Kirjat ja teokset yhdessä paikassa: 33 kirjaa, julkaisuja vuosilta 1996-2025, suosituimpien joukossa HW/SW Implementation trade-offs of MPEG-4 Data-Flow Algorithm. Vertaile teosten hintoja ja tarkista saatavuus suomalaisista kirjakaupoista.

33 kirjaa

Kirjojen julkaisuhaarukka 1996-2025.

SRAM Design for Wireless Sensor Networks

SRAM Design for Wireless Sensor Networks

Vibhu Sharma; Francky Catthoor; Wim Dehaene

Springer-Verlag New York Inc.
2012
sidottu
This book features various, ultra low energy, variability resilient SRAM circuit design techniques for wireless sensor network applications. Conventional SRAM design targets area efficiency and high performance at the increased cost of energy consumption, making it unsuitable for computation-intensive sensor node applications. This book, therefore, guides the reader through different techniques at the circuit level for reducing energy consumption and increasing the variability resilience. It includes a detailed review of the most efficient circuit design techniques and trade-offs, introduces new memory architecture techniques, sense amplifier circuits and voltage optimization methods for reducing the impact of variability for the advanced technology nodes.
Custom Memory Management Methodology

Custom Memory Management Methodology

Francky Catthoor; Sven Wuytack; G.E. de Greef; Florin Banica; Lode Nachtergaele; Arnout Vandecappelle

Springer-Verlag New York Inc.
2010
nidottu
The main intention of this book is to give an impression of the state-of-the-art in system-level memory management (data transfer and storage) related issues for complex data-dominated real-time signal and data processing applications. The material is based on research at IMEC in this area in the period 1989- 1997. In order to deal with the stringent timing requirements and the data dominated characteristics of this domain, we have adopted a target architecture style and a systematic methodology to make the exploration and optimization of such systems feasible. Our approach is also very heavily application­ driven which is illustrated by several realistic demonstrators, partly used as red-thread examples in the book. Moreover, the book addresses only the steps above the traditional high-level synthesis (scheduling and allocation) or compilation (traditional or ILP oriented) tasks. The latter are mainly focussed on scalar or scalar stream operations and data where the internal structure of the complex data types is not exploited, in contrast to the approaches discussed here. The proposed methodologies are largely independent of the level of programmability in the data-path and controller so they are valuable for the realisation of both hardware and software systems. Our target domain consists of signal and data processing systems which deal with large amounts of data.
Data Access and Storage Management for Embedded Programmable Processors

Data Access and Storage Management for Embedded Programmable Processors

Francky Catthoor; K. Danckaert; K.K. Kulkarni; E. Brockmeyer; Per Gunnar Kjeldsberg; T. van Achteren; Thierry Omnes

Springer-Verlag New York Inc.
2010
nidottu
Data Access and Storage Management for Embedded Programmable Processors gives an overview of the state-of-the-art in system-level data access and storage management for embedded programmable processors. The targeted application domain covers complex embedded real-time multi-media and communication applications. Many of these applications are data-dominated in the sense that their cost related aspects, namely power consumption and footprint are heavily influenced (if not dominated) by the data access and storage aspects. The material is mainly based on research at IMEC in this area in the period 1996-2001. In order to deal with the stringent timing requirements and the data dominated characteristics of this domain, we have adopted a target architecture style that is compatible with modern embedded processors, and we have developed a systematic step-wise methodology to make the exploration and optimization of such applications feasible in a source-to-source precompilation approach.
Systematic Methodology for Real-Time Cost-Effective Mapping of Dynamic Concurrent Task-Based Systems on Heterogenous Platforms

Systematic Methodology for Real-Time Cost-Effective Mapping of Dynamic Concurrent Task-Based Systems on Heterogenous Platforms

Zhe Ma; Pol Marchal; Daniele Paolo Scarpazza; Peng Yang; Chun Wong; José Ignacio Gómez; Stefaan Himpe; Chantal Ykman-Couvreur; Francky Catthoor

Springer
2010
nidottu
The main intention of this book is to give an impression of the state of the art in energy-aware task-scheduling-related issues for very dynamic emb- ded real-time processing applications. The material is based on research at IMEC in this area in the period 1999–2006, with a very extensive state-- the-art overview. It can be viewed as a follow-up of the earlier “Modeling, veri?cation and exploration of task-level concurrency in real-time embedded systems” book [234] that was published in 1999 based on the task-level m- eling work at IMEC. In order to deal with the stringent timing requirements, the cost-sensitivity and the dynamic characteristics of our target domain, we have again adopted a target architecture style (i. e. , heterogeneous mul- processor) and a systematic methodology to make the exploration and op- mization of such systems feasible. But this time our focus is mainly on p- viding practical work ?ow out of the (abstract) general ?ow from previous book and also the relevant scheduling techniques for each step of this ?ow. Our approach is very heavily application-driven which is illustrated by several realistic demonstrators. Moreover, the book addresses only the steps above the traditional real-time operating systems (RTOS), which are mainly focused on correct solutions for dispatching tasks. Our methodology is nearly fully independent of the implementations in the RTOS so it is va- able for the realization on those existing embedded systems where legacy applications and underlying RTOS have been developed.
Ultra-Low Energy Domain-Specific Instruction-Set Processors

Ultra-Low Energy Domain-Specific Instruction-Set Processors

Francky Catthoor; Praveen Raghavan; Andy Lambrechts; Murali Jayapala; Angeliki Kritikakou; Javed Absar

Springer
2010
sidottu
Modern consumers carry many electronic devices, like a mobile phone, digital camera, GPS, PDA and an MP3 player. The functionality of each of these devices has gone through an important evolution over recent years, with a steep increase in both the number of features as in the quality of the services that they provide. However, providing the required compute power to support (an uncompromised combination of) all this functionality is highly non-trivial. Designing processors that meet the demanding requirements of future mobile devices requires the optimization of the embedded system in general and of the embedded processors in particular, as they should strike the correct balance between flexibility, energy efficiency and performance. In general, a designer will try to minimize the energy consumption (as far as needed) for a given performance, with a sufficient flexibility. However, achieving this goal is already complex when looking at the processor in isolation, but, in reality, the processor is a single component in a more complex system. In order to design such complex system successfully, critical decisions during the design of each individual component should take into account effect on the other parts, with a clear goal to move to a global Pareto optimum in the complete multi-dimensional exploration space. In the complex, global design of battery-operated embedded systems, the focus of Ultra-Low Energy Domain-Specific Instruction-Set Processors is on the energy-aware architecture exploration of domain-specific instruction-set processors and the co-optimization of the datapath architecture, foreground memory, and instruction memory organisation with a link to the required mapping techniques or compiler steps at the early stages of the design. By performing an extensive energy breakdown experiment for a complete embedded platform, both energy and performance bottlenecks have been identified, together with the important relations between thedifferent components. Based on this knowledge, architecture extensions are proposed for all the bottlenecks.
Systematic Methodology for Real-Time Cost-Effective Mapping of Dynamic Concurrent Task-Based Systems on Heterogenous Platforms

Systematic Methodology for Real-Time Cost-Effective Mapping of Dynamic Concurrent Task-Based Systems on Heterogenous Platforms

Zhe Ma; Pol Marchal; Daniele Paolo Scarpazza; Peng Yang; Chun Wong; José Ignacio Gómez; Stefaan Himpe; Chantal Ykman-Couvreur; Francky Catthoor

Springer-Verlag New York Inc.
2007
sidottu
The main intention of this book is to give an impression of the state of the art in energy-aware task-scheduling-related issues for very dynamic emb- ded real-time processing applications. The material is based on research at IMEC in this area in the period 1999–2006, with a very extensive state-- the-art overview. It can be viewed as a follow-up of the earlier “Modeling, veri?cation and exploration of task-level concurrency in real-time embedded systems” book [234] that was published in 1999 based on the task-level m- eling work at IMEC. In order to deal with the stringent timing requirements, the cost-sensitivity and the dynamic characteristics of our target domain, we have again adopted a target architecture style (i. e. , heterogeneous mul- processor) and a systematic methodology to make the exploration and op- mization of such systems feasible. But this time our focus is mainly on p- viding practical work ?ow out of the (abstract) general ?ow from previous book and also the relevant scheduling techniques for each step of this ?ow. Our approach is very heavily application-driven which is illustrated by several realistic demonstrators. Moreover, the book addresses only the steps above the traditional real-time operating systems (RTOS), which are mainly focused on correct solutions for dispatching tasks. Our methodology is nearly fully independent of the implementations in the RTOS so it is va- able for the realization on those existing embedded systems where legacy applications and underlying RTOS have been developed.
Data Access and Storage Management for Embedded Programmable Processors

Data Access and Storage Management for Embedded Programmable Processors

Francky Catthoor; K. Danckaert; K.K. Kulkarni; E. Brockmeyer; Per Gunnar Kjeldsberg; T. van Achteren; Thierry Omnes

Springer
2002
sidottu
Data Access and Storage Management for Embedded Programmable Processors gives an overview of the state-of-the-art in system-level data access and storage management for embedded programmable processors. The targeted application domain covers complex embedded real-time multi-media and communication applications. Many of these applications are data-dominated in the sense that their cost related aspects, namely power consumption and footprint are heavily influenced (if not dominated) by the data access and storage aspects. The material is mainly based on research at IMEC in this area in the period 1996-2001. In order to deal with the stringent timing requirements and the data dominated characteristics of this domain, we have adopted a target architecture style that is compatible with modern embedded processors, and we have developed a systematic step-wise methodology to make the exploration and optimization of such applications feasible in a source-to-source precompilation approach.
Modeling, Verification and Exploration of Task-Level Concurrency in Real-Time Embedded Systems
system is a complex object containing a significant percentage of elec­ A tronics that interacts with the Real World (physical environments, humans, etc. ) through sensing and actuating devices. A system is heterogeneous, i. e. , is characterized by the co-existence of a large number of components of disparate type and function (for example, programmable components such as micro­ processors and Digital Signal Processors (DSPs), analog components such as AID and D/A converters, sensors, transmitters and receivers). Any approach to system design today must include software concerns to be viable. In fact, it is now common knowledge that more than 70% of the development cost for complex systems such as automotive electronics and communication systems are due to software development. In addition, this percentage is increasing constantly. It has been my take for years that the so-called hardware-software co-design problem is formulated at a too low level to yield significant results in shorten­ ing design time to the point needed for next generation electronic devices and systems. The level of abstraction has to be raised to the Architecture-Function co-design problem, where Function refers to the operations that the system is supposed to carry out and Architecture is the set of supporting components for that functionality. The supporting components as we said above are heteroge­ neous and contain almost always programmable components.
Custom Memory Management Methodology

Custom Memory Management Methodology

Francky Catthoor; Sven Wuytack; G.E. de Greef; Florin Banica; Lode Nachtergaele; Arnout Vandecappelle

Springer
1998
sidottu
The main intention of this book is to give an impression of the state-of-the-art in system-level memory management (data transfer and storage) related issues for complex data-dominated real-time signal and data processing applications. The material is based on research at IMEC in this area in the period 1989- 1997. In order to deal with the stringent timing requirements and the data dominated characteristics of this domain, we have adopted a target architecture style and a systematic methodology to make the exploration and optimization of such systems feasible. Our approach is also very heavily application­ driven which is illustrated by several realistic demonstrators, partly used as red-thread examples in the book. Moreover, the book addresses only the steps above the traditional high-level synthesis (scheduling and allocation) or compilation (traditional or ILP oriented) tasks. The latter are mainly focussed on scalar or scalar stream operations and data where the internal structure of the complex data types is not exploited, in contrast to the approaches discussed here. The proposed methodologies are largely independent of the level of programmability in the data-path and controller so they are valuable for the realisation of both hardware and software systems. Our target domain consists of signal and data processing systems which deal with large amounts of data.
Accelerator Data-Path Synthesis for High-Throughput Signal Processing Applications

Accelerator Data-Path Synthesis for High-Throughput Signal Processing Applications

Werner Geurts; Francky Catthoor; Serge Vernalde; Hugo De Man

Springer
1996
sidottu
Accelerator Data-Path Synthesis for High-Throughput Signal Processing Applications is the first book to show how to use high-level synthesis techniques to cope with the stringent timing requirements of complex high-throughput real-time signal and data processing. The book describes the state-of-the-art in architectural synthesis for complex high-throughput real-time processing. Unlike many other, the Synthesis approach used in this book targets an architecture style or an application domain. This approach is thus heavily application-driven and this is illustrated in the book by several realistic demonstration examples used throughout. Accelerator Data-Path Synthesis for High-Throughput Signal Processing Applications focuses on domains where application-specific high-speed solutions are attractive such as significant parts of audio, telecom, instrumentation, speech, robotics, medical and automotive processing, image and video processing, TV, multi-media, radar, sonar, etc. Moreover, it addresses mainly the steps above the traditional scheduling and allocation tasks which focus on scalar operations and data. Accelerator Data-Path Synthesis for High-Throughput Signal Processing Applications is of interest to researchers, senior design engineers and CAD managers both in academia and industry. It provides an excellent overview of what capabilities to expect from future practical design tools and includes an extensive bibliography.