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Marc Manzano

Kirjat ja teokset yhdessä paikassa: 2 kirjaa, julkaisuja vuosilta 2020-2021, suosituimpien joukossa Hardware Architectures for Post-Quantum Digital Signature Schemes. Vertaile teosten hintoja ja tarkista saatavuus suomalaisista kirjakaupoista.

2 kirjaa

Kirjojen julkaisuhaarukka 2020-2021.

Hardware Architectures for Post-Quantum Digital Signature Schemes

Hardware Architectures for Post-Quantum Digital Signature Schemes

Deepraj Soni; Kanad Basu; Mohammed Nabeel; Najwa Aaraj; Marc Manzano; Ramesh Karri

Springer Nature Switzerland AG
2021
nidottu
This book explores C-based design, implementation, and analysis of post-quantum cryptography (PQC) algorithms for signature generation and verification. The authors investigate NIST round 2 PQC algorithms for signature generation and signature verification from a hardware implementation perspective, especially focusing on C-based design, power-performance-area-security (PPAS) trade-offs and design flows targeting FPGAs and ASICs.Describes a comprehensive set of synthesizable c code base as well as the hardware implementations for the different types of PQC algorithms including lattice-based, code-based, and multivariate-based;Demonstrates the hardware (FPGA and ASIC) and hardware-software optimizations and trade-offs of the NIST round 2 signature-based PQC algorithms;Enables designers to build hardware implementations that are resilient to a variety of side-channels.
Hardware Architectures for Post-Quantum Digital Signature Schemes

Hardware Architectures for Post-Quantum Digital Signature Schemes

Deepraj Soni; Kanad Basu; Mohammed Nabeel; Najwa Aaraj; Marc Manzano; Ramesh Karri

Springer Nature Switzerland AG
2020
sidottu
This book explores C-based design, implementation, and analysis of post-quantum cryptography (PQC) algorithms for signature generation and verification. The authors investigate NIST round 2 PQC algorithms for signature generation and signature verification from a hardware implementation perspective, especially focusing on C-based design, power-performance-area-security (PPAS) trade-offs and design flows targeting FPGAs and ASICs.Describes a comprehensive set of synthesizable c code base as well as the hardware implementations for the different types of PQC algorithms including lattice-based, code-based, and multivariate-based;Demonstrates the hardware (FPGA and ASIC) and hardware-software optimizations and trade-offs of the NIST round 2 signature-based PQC algorithms;Enables designers to build hardware implementations that are resilient to a variety of side-channels.