Massimo Alioto

This book offers the first comprehensive coverage of digital design techniques to expand the power-performance tradeoff well beyond that allowed by conventional wide voltage scaling. Compared to conventional fixed designs, the approach described in this book makes digital circuits more versatile and adaptive, allowing simultaneous optimization at both ends of the power-performance spectrum. Drop-in solutions for fully automated and low-effort design based on commercial CAD tools are discussed extensively for processors, accelerators and on-chip memories, and are applicable to prominent applications (e.g., IoT, AI, wearables, biomedical). Through the higher power-performance versatility techniques described in this book, readers are enabled to reduce the design effort through reuse of the same digital design instance, across a wide range of applications. All concepts the authors discuss are demonstrated by dedicated testchip designs and experimental results. To make the results immediately usable by the reader, all the scripts necessary to create automated design flows based on commercial tools are provided and explained.

This book offers the first comprehensive coverage of digital design techniques to expand the power-performance tradeoff well beyond that allowed by conventional wide voltage scaling. Compared to conventional fixed designs, the approach described in this book makes digital circuits more versatile and adaptive, allowing simultaneous optimization at both ends of the power-performance spectrum. Drop-in solutions for fully automated and low-effort design based on commercial CAD tools are discussed extensively for processors, accelerators and on-chip memories, and are applicable to prominent applications (e.g., IoT, AI, wearables, biomedical). Through the higher power-performance versatility techniques described in this book, readers are enabled to reduce the design effort through reuse of the same digital design instance, across a wide range of applications. All concepts the authors discuss are demonstrated by dedicated testchip designs and experimental results. To make the results immediately usable by the reader, all the scripts necessary to create automated design flows based on commercial tools are provided and explained.

This book provides a unified treatment of Flip-Flop design and selection in nanometer CMOS VLSI systems. The design aspects related to the energy-delay tradeoff in Flip-Flops are discussed, including their energy-optimal selection according to the targeted application, and the detailed circuit design in nanometer CMOS VLSI systems. Design strategies are derived in a coherent framework that includes explicitly nanometer effects, including leakage, layout parasitics and process/voltage/temperature variations, as main advances over the existing body of work in the field. The related design tradeoffs are explored in a wide range of applications and the related energy-performance targets. A wide range of existing and recently proposed Flip-Flop topologies are discussed. Theoretical foundations are provided to set the stage for the derivation of design guidelines, and emphasis is given on practical aspects and consequences of the presented results. Analytical models and derivations are introduced when needed to gain an insight into the inter-dependence of design parameters under practical constraints. This book serves as a valuable reference for practicing engineers working in the VLSI design area, and as text book for senior undergraduate, graduate and postgraduate students (already familiar with digital circuits and timing).

This book provides a unified treatment of Flip-Flop design and selection in nanometer CMOS VLSI systems. The design aspects related to the energy-delay tradeoff in Flip-Flops are discussed, including their energy-optimal selection according to the targeted application, and the detailed circuit design in nanometer CMOS VLSI systems. Design strategies are derived in a coherent framework that includes explicitly nanometer effects, including leakage, layout parasitics and process/voltage/temperature variations, as main advances over the existing body of work in the field. The related design tradeoffs are explored in a wide range of applications and the related energy-performance targets. A wide range of existing and recently proposed Flip-Flop topologies are discussed. Theoretical foundations are provided to set the stage for the derivation of design guidelines, and emphasis is given on practical aspects and consequences of the presented results. Analytical models and derivations are introduced when needed to gain an insight into the inter-dependence of design parameters under practical constraints. This book serves as a valuable reference for practicing engineers working in the VLSI design area, and as text book for senior undergraduate, graduate and postgraduate students (already familiar with digital circuits and timing).

Current-Mode digital circuits have been extensively analyzed and used since the early days of digital ICs. In particular, bipolar Current-Mode digital circuits emerged as an approach to realize digital circuits with the highest speed. Together with its speed performance, CMOS Current-Mode logic has been rediscovered to allow logic gates implementations which, in contrast to classical VLSI CMOS digital circuits, have the feature of low noise level generation. Thus, CMOS Current-Mode gates can be efficiently used inside analog and mixed-signal ICs, which require a low noise silicon environment. For these reasons, until today, many works and results have been published which reinforce the importance of Current-Mode digital circuits. In the topic of Current-Mode digital circuits, the authors spent a lot of effort in the last six years, and their original results highly enhanced both the modeling and the related design methodologies. Since the fundamental Current-Mode logic building block is the classical differential amplifier, the winning idea, that represents the starting point of the authors’ research, was to change the classical point of view typically followed in the investigation and design of Current-Mode digital circuits. In particular, they properly exploited classical paradigms developed and used in the analog circuit domain (a topic in which one of the authors maturated a great experience).

Current-Mode digital circuits have been extensively analyzed and used since the early days of digital ICs. In particular, bipolar Current-Mode digital circuits emerged as an approach to realize digital circuits with the highest speed. Together with its speed performance, CMOS Current-Mode logic has been rediscovered to allow logic gates implementations which, in contrast to classical VLSI CMOS digital circuits, have the feature of low noise level generation. Thus, CMOS Current-Mode gates can be efficiently used inside analog and mixed-signal ICs, which require a low noise silicon environment. For these reasons, until today, many works and results have been published which reinforce the importance of Current-Mode digital circuits. In the topic of Current-Mode digital circuits, the authors spent a lot of effort in the last six years, and their original results highly enhanced both the modeling and the related design methodologies. Since the fundamental Current-Mode logic building block is the classical differential amplifier, the winning idea, that represents the starting point of the authors’ research, was to change the classical point of view typically followed in the investigation and design of Current-Mode digital circuits. In particular, they properly exploited classical paradigms developed and used in the analog circuit domain (a topic in which one of the authors maturated a great experience).