Michiel Steyaert

This book describes the design of optical receivers that use the most economical integration technology, while enabling performance that is typically only found in very expensive devices. To achieve this, all necessary functionality, from light detection to digital output, is integrated on a single piece of silicon. All building blocks are thoroughly discussed, including photodiodes, transimpedance amplifiers, equalizers and post amplifiers.

CMOS DC-DC Converters aims to provide a comprehensive dissertation on the matter of monolithic inductive Direct-Current to Direct-Current (DC-DC) converters. For this purpose seven chapters are defined which will allow the designer to gain specific knowledge on the design and implementation of monolithic inductive DC-DC converters, starting from the very basics.

This work investigates the feasibility of the integration of interface circuits for op­ tical communication systems in a standard unmodified digital CMOS process. This paves the way for single chip communication systems where the optical interfaces are integrated on the same die as the required digital circuitry. The optical receiver is a key element in the optical communication link. In this work, a transimpedance amplifier, which consists of a voltage amplifier with resis­ tive feedback, is used as the first stage. Unlike for many other circuits, the optimal place of its dominant pole is the input node. It is also demonstrated that a high gain of the voltage amplifier is primordial to obtain good performances and that this may be obtained through the use of multiple stages. Noise aspects are investigated and the conclusion is drawn that the amplifier's input capacitance can be smaller than the photodiode's capacitance for optimal performance.

Design and Analysis of High Efficiency Line Drivers for xDSL covers the most important building block of an xDSL (ADSL, VDSL, ...) system: the line driver. Traditional Class AB line drivers consume more than 70% of the total power budget of state-of-the-art ADSL modems. This book describes the main difficulties in designing line drivers for xDSL. The most important specifications are elaborated staring from the main properties of the channel and the signal properties. The traditional (class AB), state-of-the-art (class G) and future technologies (class K) are discussed. The main part of Design and Analysis of High Efficiency Line Drivers for xDSL describes the design of a novel architecture: the Self-Oscillating Power Amplifier or SOPA.

Static and Dynamic Performance Limitations for High Speed D/A Converters discusses the design and implementation of high speed current-steering CMOS digital-to-analog converters. Starting from the definition of the basic specifications for a D/A converter, the elements determining the static and dynamic performance are identified. Different guidelines based on scientific derivations are suggested to optimize this performance. Furthermore, a new closed formula has been derived to account for the influence of the transistor mismatch on the achievable resolution of the current-steering D/A converter. To allow a thorough understanding of the dynamic behavior, a new factor has been introduced. Moreover, the frequency dependency of the output impedance introduces harmonic distortion components which can limit the maximum attainable spurious free dynamic range. Finally, the last part of the book gives an overview on different existing transistor mismatch models and the link with the static performance of the D/A converter.

Design of Low-Voltage Low-Power CMOS Delta-Sigma A/D Converters investigates the feasibility of designing Delta-Sigma Analog to Digital Converters for very low supply voltage (lower than 1.5V) and low power operation in standard CMOS processes. The chosen technique of implementation is the Switched Opamp Technique which provides Switched Capacitor operation at low supply voltage without the need to apply voltage multipliers or low VtMOST devices. A method of implementing the classic single loop and cascaded Delta-Sigma modulator topologies with half delay integrators is presented. Those topologies are studied in order to find the parameters that maximise the performance in terms of peak SNR. Based on a linear model, the performance degradations of higher order single loop and cascaded modulators, compared to a hypothetical ideal modulator, are quantified. An overview of low voltage Switched Capacitor design techniques, such as the use of voltage multipliers, low VtMOST devices and the Switched Opamp Technique, is given. An in-depth discussion of the present status of the Switched Opamp Technique covers the single-ended Original Switched Opamp Technique, the Modified Switched Opamp Technique, which allows lower supply voltage operation, and differential implementation including common mode control techniques. The restrictions imposed on the analog circuits by low supply voltage operation are investigated. Several low voltage circuit building blocks, some of which are new, are discussed. A new low voltage class AB OTA, especially suited for differential Switched Opamp applications, together with a common mode feedback amplifier and a comparator are presented and analyzed. As part of a systematic top-down design approach, the non-ideal charge transfer of the Switched Opamp integrator cell is modeled, based upon several models of the main opamp non-ideal characteristics. Behavioral simulations carried out with these models yield the required opamp specifications that ensure that the intended performance is met in an implementation. A power consumption analysis is performed. The influence of all design parameters, especially the low power supply voltage, is highlighted. Design guidelines towards low power operation are distilled. Two implementations are presented together with measurement results. The first one is a single-ended implementation of a Delta-Sigma ADC operating with 1.5V supply voltage and consuming 100 &mgr;W for a 74 dB dynamic range in a 3.4 kHz bandwidth. The second implementation is differential and operates with 900 mV. It achieves 77 dB dynamic range in 16 kHz bandwidth and consumes 40 &mgr;W. Design of Low-Voltage Low-Power CMOS Delta-Sigma A/D Converters is essential reading for analog design engineers and researchers.

The recent boom in the mobile telecommunication market has trapped the interest of almost all electronic and communication companies worldwide. New applications arise every day, more and more countries are covered by digital cellular systems and the competition between the several providers has caused prices to drop rapidly. The creation of this essentially new market would not have been possible without the ap­ pearance of smalI, low-power, high-performant and certainly low-cost mobile termi­ nals. The evolution in microelectronics has played a dominant role in this by creating digital signal processing (DSP) chips with more and more computing power and com­ bining the discrete components of the RF front-end on a few ICs. This work is situated in this last area, i. e. the study of the full integration of the RF transceiver on a single die. Furthermore, in order to be compatible with the digital processing technology, a standard CMOS process without tuning, trimming or post-processing steps must be used. This should flatten the road towards the ultimate goal: the single chip mobile phone. The local oscillator (LO) frequency synthesizer poses some major problems for integration and is the subject of this work. The first, and also the largest, part of this text discusses the design of the Voltage­ Controlled Oscillator (VCO). The general phase noise theory of LC-oscillators is pre­ sented, and the concept of effective resistance and capacitance is introduced to char­ acterize and compare the performance of different LC-tanks.

High Data Rate Transmitter Circuits is a practical guide and introduction to the design of key RF building blocks used in high data rate transmitters. The emphasis lies on CMOS circuit techniques applicable to oscillators and upconvertors. Furthermore, a method for RF-specific design automation is exemplified by the CYCLONE tool for automated LC-VCO synthesis. Written in an easily accessible manner, High Data Rate Transmitter Circuits is essential reading for both students and practicing engineers interested in analog RF design and RF-specific design automation. The book has been praised for its pleasant and light style of writing, without losing detail on the technical side.

High-Performance CMOS Continuous-Time Filters is devoted to the design of CMOS continuous-time filters. CMOS is employed because the most complex integrated circuits have been realized with this technology for two decades. The most important advantages and drawbacks of continuous-time filters are clearly shown. The transfer function is one of the most important filter parameters but several others (like intermodulation distortion, power-supply rejection ratio, noise level and dynamic range) are fundamental in the design of high-performance systems. Special attention is paid to the practical aspects of the design, which shows the difference between an academic design and an industrial design. A clear understanding of the behavior of the circuits and techniques is preferred over complex equations or interpretation of simulated results. Step-by-step design procedures are very often used to clarify the use of the techniques and topologies. The organization of this text is hierarchical, starting with the design consideration of the basic building blocks and ending with the design of several high-performance continuous-time filters. Most of the circuits have been fabricated, theoretically analyzed and simulated, and silicon measurement results are compared with each other. High-Performance CMOS Continuous-Time Filters can be used as a text book for senior or graduate courses on this topic and can also be useful for industrial engineers as a reference book.

CMOS Cellular Receiver Front-Ends: from Specification to Realization deals with the design of the receive path of a highly-integrated CMOS cellular transceiver for the GSM-1800 cellular system. The complete design trajectory is covered, starting from the documents describing the standard down to the systematic development of CMOS receiver ICs that comply to the standard. The design of CMOS receivers is tackled at all abstraction levels: from architecture level, via circuit level, down to the device level, and the other way around. The theoretical core of the book discusses the fundamental and more advanced aspects of RF CMOS design. It focuses specifically on all aspects of the design of high-performance CMOS low-noise amplifiers.

CMOS Fractional-N Synthesizers starts with a comprehensive introduction to general frequency synthesis. Different architectures and synthesizer building blocks are discussed with their relative importance on synthesizer specifications. The process of synthesizer specification derivation is illustrated with the DCS-1800 standard as a general test case. The book tackles the design of fractional-N synthesizers in CMOS on circuit level as well as system level. The circuit level focuses on high-speed prescaler design up to 12 GHz in CMOS and on fully integrated, low-phase-noise LC-VCO design. High-Q inductor integration and simulation in CMOS is elaborated and flicker noise minimization techniques are presented, ranging from bias point choice to noise filtering techniques. On a higher level, a systematic design strategy has been developed that trades off all noise contributions and fast dynamics for integrated capacitance (area). Moreover, a theoretical DeltaSigma phase noise analysis is presented, extended with a fast non-linear analysis method to accurately predict the influence of PLL non-linearities on the spectral purity of the DeltaSigma fractional-N frequency synthesizers.

When comparing conventional computing architectures to the architectures of biological neural systems, we find several striking differences. Conventional computers use a low number of high performance computing elements that are programmed with algorithms to perform tasks in a time sequenced way; they are very successful in administrative applications, in scientific simulations, and in certain signal processing applications. However, the biological systems still significantly outperform conventional computers in perception tasks, sensory data processing and motory control. Biological systems use a completely dif­ ferent computing paradigm: a massive network of simple processors that are (adaptively) interconnected and operate in parallel. Exactly this massively parallel processing seems the key aspect to their success. On the other hand the development of VLSI technologies provide us with technological means to implement very complicated systems on a silicon die. Especially analog VLSI circuits in standard digital technologies open the way for the implement at ion of massively parallel analog signal processing systems for sensory signal processing applications and for perception tasks. In chapter 1 the motivations behind the emergence of the analog VLSI of massively parallel systems is discussed in detail together with the capabilities and !imitations of VLSI technologies and the required research and developments. Analog parallel signal processing drives for the development of very com­ pact, high speed and low power circuits. An important technologicallimitation in the reduction of the size of circuits and the improvement of the speed and power consumption performance is the device inaccuracies or device mismatch.

The world of wireless communications is changing very rapidly since a few years. The introduction of digital data communication in combination with digital signal process­ ing has created the foundation for the development of many new wireless applications. High-quality digital wireless networks for voice communication with global and local coverage, like the GSM and DECT system, are only faint and early examples of the wide variety of wireless applications that will become available in the remainder of this decade. The new evolutions in wireless communications set new requirements for the trans­ ceivers (transmitter-receivers). Higher operating frequencies, a lower power consump­ tion and a very high degree of integration, are new specifications which ask for design approaches quite different from the classical RF design techniques. The integrata­ bility and power consumption reduction of the digital part will further improve with the continued downscaling of technologies. This is however completely different for the analog transceiver front-end, the part which performs the interfacing between the antenna and the digital signal processing. The analog front-end's integratability and power consumption are closely related to the physical limitations of the transceiver topology and not so much to the scaling of the used technology. Chapter 2 gives a detailed study of the level of integration in current transceiver realization and analyzes their limitations. In chapter 3 of this book the complex signal technique for the analysis and synthesis of multi-path receiver and transmitter topologies is introduced.

RF Power Amplifiers for Mobile Communications fits in the quest for fully integrated CMOS transceivers. The book tackles both high efficiency and high linearity PA design in low-voltage CMOS, and has a strong emphasis on theory, design and implementation. The book is conceived as a design guide for those actively involved in the design of CMOS wireless transceivers. RF Power Amplifiers for Mobile Communications starts from the basic theory of power amplification from the viewpoint of CMOS integration. The design of switching RF power amplifiers in CMOS is explored and CMOS PA design at low supply voltage using parallel amplification is discussed. Combining both efficiency and linearity is one of the major issues in CMOS PA design for wireless and mobile communications and is subsequently tackled. Different linearization techniques and approaches are discussed and polar modulation is clarified in greater detail. Finally, two CMOS PAimplementations are thoroughly covered. RF Power Amplifiers for Mobile Communications offers the reader an intuitive insight in Power Amplification as well as the necessary mathematical background. The book is essential reading for RF design engineers and researchers in the field and is also suitable as a text book for an advanced course on the subject.

“Design of high voltage xDSL line drivers in standard CMOS” fits in the quest for highly efficient fully integrated xDSL modems for central office applications. The book focusses on the line driver, the most demanding building block of the xDSL modem for lowering power. To reduce the cost, the cheapest technology is selected: standard CMOS, without any extra process options to increase the nominal supply voltage. The emphasis lies on the analysis, design and implementation of high voltage highly efficient line drivers in mainstream CMOS. “Design of high voltage xDSL line drivers in standard CMOS” covers the total design flow of monolithic CMOS high voltage circuits. The book is essential reading for analog design engineers and researchers in the field and is also suitable as a text book for an advanced course on the subject.

Broadband Opto-Electrical Receivers in Standard CMOS starts from the basic fundamentals necessary for the design of opto-electronic interface circuits. The book continues with an in-depth analysis of the photodiode, transimpedance amplifier (TIA) and limiting amplifier (LA). To thoroughly understand the light detection mechanisms in silicon, first a one-dimensional and second a two-dimensional model is developed. Analytical design equations are derived to guide the design of the amplifying circuits. For the TIA, the focus is on the sensitivity-speed trade-off. For the LA, a high gain-bandwidth is pursued. Several practical design examples reveal the subtleties and challenges encountered during the design of high-performance analog circuits. Broadband Opto-Electrical Receivers in Standard CMOS covers the total design flow of monolithic CMOS optical receivers. All material is experimentally verified with several CMOS implementations, with ultimately a fully integrated Gbit/s optical receiver front-end including photodiode, TIA and LA.

Low-Power Low-Voltage Sigma-Delta Modulators in Nanometer CMOS addresses the low-power low-voltage Sigma-Delta ADC design in nanometer CMOS technologies at both the circuit-level and the system level. The low-power low-voltage Sigma-Delta modulator design at the circuit level is introduced. A design example is presented in this book. This design is the first published Sigma-Delta design in a 90-nm CMOS technology and reaches a very high figure-of-merit. At the system level, a novel systematic study on the full feedforward Sigma-Delta topology is presented in this book. As a design example, a fourth-order single-loop full feedforward Sigma-Delta modulator design in a 130-nm pure digital CMOS technology is presented. This design is the first design using the full feedforward Sigma-Delta topology and reaches the highest conversion speed among all the 1-V Sigma-Delta modulators to date.

Today’s booming expanse of personal wireless radio communications is a rich source of new challenges for the designer of the underlying enabling te- nologies. Personal communication networks are designed from a fundam- tally different perspective than broadcast service networks, such as radio and television. While the focus of the latter is on reliability and user comfort, the emphasis of personal communication devices is on throughput and mobility. However, because the wireless channel is a shared transmission medium with only very limited resources, a trade-off has to be made between mobility and the number of simultaneous users in a con?ned geographical area. Accord- 1 ing to Shannon’s theorem on channel capacity, the overall data throughput of a communication channel bene?ts from either a linear increase of the tra- mission bandwidth, or an (equivalent) exponential increase in signal quality. Consequently, it is more bene?cial to think in terms of channel bandwidth than it is to pursue a high transmission power. All the above elements are embodied in the concept of spatial ef?ciency. By describing the throughput of a system 2 in terms of bits/s/Hz/m , spatial ef?ciency takes into account that the use of a low transmission power reduces the operational range of a radio transmission, and as such enables a higher reuse rate of the same frequency spectrum.

Environmental electromagnetic pollution has drastically increased over the last decades. The omnipresence of communication systems, various electronic appliances and the use of ever increasing frequencies, all contribute to a noisy electromagnetic environment which acts detrimentally on sensitive electronic equipment. Integrated circuits must be able to operate satisfactorily while cohabiting harmoniously in the same appliance, and not generate intolerable levels of electromagnetic emission, while maintaining a sound immunity to potential electromagnetic disturbances: analog integrated circuits are in particular more easily disturbed than their digital counterparts, since they don't have the benefit of dealing with predefined levels ensuring an innate immunity to disturbances. The objective of the research domain presented in EMC of Analog Integrated Circuits is to improve the electromagnetic immunity of considered analog integrated circuits, so that they start to fail at relevantly higher conduction levels than before.

This book describes new tools for front end analog designers, starting with global variation-aware sizing, and extending to novel variation-aware topology design. The tools aid design through automation, but more importantly, they also aid designer insight through automation. We now describe four design tasks, each more general than the previous, and how this book contributes design aids and insight aids to each. The ?rst designer task targeted is global robust sizing. This task is supported by a design tool that does automated, globally reliable, variation-aware s- ing (SANGRIA),and an insight-aiding tool that extracts designer-interpretable whitebox models that relate sizings to circuit performance (CAFFEINE). SANGRIA searches on several levels of problem dif?culty simultaneously, from lower cheap-to-evaluate “exploration” layers to higher full-evaluation “exploitation” layers (structural homotopy). SANGRIAmakes maximal use of circuit simulations by performing scalable data mining on simulation results to choose new candidate designs. CAFFEINE accomplishes its task by tre- ing function induction as a tree-search problem. It constrains its tree search space via a canonical-functional-form grammar, and searches the space with grammatically constrained genetic programming. The second designer task is topology selection/topology design. Topology selection tools must consider a broad variety of topologies such that an app- priate topology is selected, must easily adapt to new semiconductor process nodes, and readily incorporate new topologies. Topology design tools must allow designers to creatively explore new topology ideas as rapidly as possible.