Peter Marwedel

A unique feature of this open access textbook is to provide a comprehensive introduction to the fundamental knowledge in embedded systems, with applications in cyber-physical systems and the Internet of things. It starts with an introduction to the field and a survey of specification models and languages for embedded and cyber-physical systems. It provides a brief overview of hardware devices used for such systems and presents the essentials of system software for embedded systems, including real-time operating systems. The author also discusses evaluation and validation techniques for embedded systems and provides an overview of techniques for mapping applications to execution platforms, including multi-core platforms. Embedded systems have to operate under tight constraints and, hence, the book also contains a selected set of optimization techniques, including software optimization techniques. The book closes with a brief survey on testing. This fourth edition has been updated andrevised to reflect new trends and technologies, such as the importance of cyber-physical systems (CPS) and the Internet of things (IoT), the evolution of single-core processors to multi-core processors, and the increased importance of energy efficiency and thermal issues.

Ein Alleinstellungsmerkmal dieses Open-Access-Lehrbuchs ist die umfassende Einführung in das Grundlagenwissen über eingebettete Systeme mit Anwendungen in cyber-physischen Systemen und dem Internet der Dinge. Es beginnt mit einer Einführung in das Gebiet und eine Übersicht über Spezifikationsmodelle und -sprachen für eingebettete und cyber-physikalische Systeme. Es gibt einen kurzen Überblick über die für solche Systeme verwendeten Hardware-Geräte und stellt die Grundlagen der Systemsoftware für eingebettete Systeme vor, einschließlich Echtzeit-Betriebssystemen. Der Autor erörtert auch Evaluierungs- und Validierungstechniken für eingebettete Systeme und gibt einen Überblick über Techniken zur Abbildung von Anwendungen auf Ausführungsplattformen, inklusive Multi-Core-Plattformen. Eingebettete Systeme müssen unter engen Randbedingungen arbeiten, daher enthält das Buch auch einen ausgewählten Satz von Optimierungstechniken, mit einem Schwerpunkt bei Software-Optimierungstechniken. Das Buch schließt mit einer kurzen Übersicht über das Testen. Die vierte Auflage wurde aktualisiert und überarbeitet, um neue Trends und Technologien zu berücksichtigen, wie z. B. die Bedeutung von cyber-physischen Systemen (CPS) und dem Internet der Dinge (IoT), die Entwicklung von Single-Core-Prozessoren hin zu Multi-Core-Prozessoren und die zunehmende Bedeutung von Energieeffizienz und thermischen Fragen.

A unique feature of this open access textbook is to provide a comprehensive introduction to the fundamental knowledge in embedded systems, with applications in cyber-physical systems and the Internet of things. It starts with an introduction to the field and a survey of specification models and languages for embedded and cyber-physical systems. It provides a brief overview of hardware devices used for such systems and presents the essentials of system software for embedded systems, including real-time operating systems. The author also discusses evaluation and validation techniques for embedded systems and provides an overview of techniques for mapping applications to execution platforms, including multi-core platforms. Embedded systems have to operate under tight constraints and, hence, the book also contains a selected set of optimization techniques, including software optimization techniques. The book closes with a brief survey on testing. This fourth edition has been updated andrevised to reflect new trends and technologies, such as the importance of cyber-physical systems (CPS) and the Internet of things (IoT), the evolution of single-core processors to multi-core processors, and the increased importance of energy efficiency and thermal issues.

A unique feature of this textbook is to provide a comprehensive introduction to the fundamental knowledge in embedded systems, with applications in cyber-physical systems and the Internet of things. It starts with an introduction to the field and a survey of specification models and languages for embedded and cyber-physical systems. It provides a brief overview of hardware devices used for such systems and presents the essentials of system software for embedded systems, including real-time operating systems. The author also discusses evaluation and validation techniques for embedded systems and provides an overview of techniques for mapping applications to execution platforms, including multi-core platforms. Embedded systems have to operate under tight constraints and, hence, the book also contains a selected set of optimization techniques, including software optimization techniques. The book closes with a brief survey on testing. This third edition has been updated and revised to reflect new trends and technologies, such as the importance of cyber-physical systems and the Internet of things, the evolution of single-core processors to multi-core processors, and the increased importance of energy efficiency and thermal issues.

For real-time systems, the worst-case execution time (WCET) is the key objective to be considered. Traditionally, code for real-time systems is generated without taking this objective into account and the WCET is computed only after code generation. Worst-Case Execution Time Aware Compilation Techniques for Real-Time Systems presents the first comprehensive approach integrating WCET considerations into the code generation process. Based on the proposed reconciliation between a compiler and a timing analyzer, a wide range of novel optimization techniques is provided. Among others, the techniques cover source code and assembly level optimizations, exploit machine learning techniques and address the design of modern systems that have to meet multiple objectives. Using these optimizations, the WCET of real-time applications can be reduced by about 30% to 45% on the average. This opens opportunities for decreasing clock speeds, costs and energy consumption of embedded processors. The proposed techniques can be used for all types real-time systems, including automotive and avionics IT systems.

This book focuses on source-to-source code transformations that remove addressing-related overhead present in most multimedia or signal processing application programs. This approach is complementary to existing compiler technology. What is particularly attractive about the transformation flow pre­ sented here is that its behavior is nearly independent of the target processor platform and the underlying compiler. Hence, the different source code trans­ formations developed here lead to impressive performance improvements on most existing processor architecture styles, ranging from RISCs like ARM7 or MIPS over Superscalars like Intel-Pentium, PowerPC, DEC-Alpha, Sun and HP, to VLIW DSPs like TI C6x and Philips TriMedia. The source code did not have to be modified between processors to obtain these results. Apart from the performance improvements, the estimated energy is also significantly reduced for a given application run. These results were not obtained for academic codes but for realistic and rep­ resentative applications, all selected from the multimedia domain. That shows the industrial relevance and importance of this research. At the same time, the scientific novelty and quality of the contributions have lead to several excellent papers that have been published in internationally renowned conferences like e. g. DATE. This book is hence of interest for academic researchers, both because of the overall description of the methodology and related work context and for the detailed descriptions of the compilation techniques and algorithms.

It is well known that embedded systems have to be implemented efficiently. This requires that processors optimized for certain application domains are used in embedded systems. Such an optimization requires a careful exploration of the design space, including a detailed study of cost/performance tradeoffs. In order to avoid time-consuming assembly language programming during design space exploration, compilers are needed. In order to analyze the effect of various software or hardware configurations on the performance, retargetable compilers are needed that can generate code for numerous different potential hardware configurations. This book provides a comprehensive and up-to-date overview of the fast developing area of retargetable compilers for embedded systems. It describes a large set important tools as well as applications of retargetable compilers at different levels in the design flow. Retargetable Compiler Technology for Embedded Systems is mostly self-contained and requires only fundamental knowledge in software and compiler design. It is intended to be a key reference for researchers and designers working on software, compilers, and processor optimization for embedded systems.

Many of the modern applications of microelectronics require hugeamounts of computations. Despite all recent improvements in fabrication technologies, some of these computations have to be performed in hardware in order to meet deadlines. However, controlling computations by software is frequently pre­ ferred due to the larger flexibility. Hence, in general, modern applications re­ quire a mix of software-based and hardware-based computations. Applications using this mix can be designed with the help of hardware/software co-design systems. Many such co-design systems have been described so far (references can be found in this book), but many of these are based on heuristics. In this book, Niemann describes a co-design system which is based on sound modeling techniques. This system has the following salient features: • Precise cost and performance figures Design decisions for implementing a certain function in hardware or software are based on 'cost and performance figures for the different design alterna­ tives. Hence, good designs can only be expected if these figures are accurate. In order to achieve excellent accuracy, Niemann takes a new approach: the cost of software implementations is derived from the data available about the target processors and from knowledge about the code size. the performance of software implement at ions is computed by compiling the given function and then using static analysis for computing worst case execution times. the cost of hardware implementation is estimated by running higher-Ievel synthesis tools. the performance of hardware implementations is again computed by us­ ing static analysis.

Fast, Efficient and Predictable Memory Accesses presents techniques for designing fast, energy-efficient and timing predictable memory systems. By using a careful combination of compiler optimizations and architectural improvements, we can achieve more than what would be feasible at one of the levels in isolation. The described optimization algorithms achieve the goals of high performance and low energy consumption. In addition to these benefits, the use of scratchpad memories significantly improves the timing predictability of the entire system, leading to tighter worst case execution time bounds (WCET). The WCET is a relevant design parameter for all timing critical systems. In addition, the book covers algorithms to exploit the power down modes of main memories in SDRAM technology, as well as the execute-in-place feature of Flash memories. The final chapter considers the impact of the register file, which is also part of the memory hierarchy.

In a relatively short span of time, computers have evolved from huge mainframes to small and elegant desktop computers, and now to low-power, ultra-portable handheld devices. Witheachpassinggeneration,computersconsistingofprocessors,memoriesandperipherals becamesmallerandfaster.Forexample,the?rstcommercialcomputerUNIVACIcosted $1 million dollars, occupied 943 cubic feet space and could perform 1,905 operations per second [94]. Now, a processor present in an electric shaver easily outperforms the early mainframe computers. The miniaturization is largely due to the efforts of engineers and scientists that made the expeditious progress in the microelectronic technologies possible. According to Moore’s Law [90], the advances in technology allow us to double the number of transistors on a single silicon chip every 18 months. This has lead to an exponential increase in the number of transistors on a chip, from 2,300 in an Intel 4004 to 42 millions in Intel Itanium processor [55]. Moore’s Law has withstood for 40 years and is predicted to remain valid for at least another decade [91]. Notonlytheminiaturizationanddramaticperformanceimprovementbutalsothesign- icantdropinthepriceofprocessors,hasleadtosituationwheretheyarebeingintegratedinto products, such as cars, televisions and phones which are not usually associated with c- puters.This new trend has also been called the disappearing computer, where the computer does not actually disappear but it is everywhere [85]. Digital devices containing processors now constitute a major part of our daily lives. Asmalllistofsuchdevicesincludesmicrowaveovens,televisionsets,mobilephones,digital cameras, MP3 players and cars. Whenever a system comprises of information processingdigitaldevicestocontrolortoaugmentitsfunctionality,suchasystemistermedanembedded system. Therefore, all the above listed devices can be also classi?ed as embedded systems.

For real-time systems, the worst-case execution time (WCET) is the key objective to be considered. Traditionally, code for real-time systems is generated without taking this objective into account and the WCET is computed only after code generation. Worst-Case Execution Time Aware Compilation Techniques for Real-Time Systems presents the first comprehensive approach integrating WCET considerations into the code generation process. Based on the proposed reconciliation between a compiler and a timing analyzer, a wide range of novel optimization techniques is provided. Among others, the techniques cover source code and assembly level optimizations, exploit machine learning techniques and address the design of modern systems that have to meet multiple objectives. Using these optimizations, the WCET of real-time applications can be reduced by about 30% to 45% on the average. This opens opportunities for decreasing clock speeds, costs and energy consumption of embedded processors. The proposed techniques can be used for all types real-time systems, including automotive and avionics IT systems.

In a relatively short span of time, computers have evolved from huge mainframes to small and elegant desktop computers, and now to low-power, ultra-portable handheld devices. Witheachpassinggeneration,computersconsistingofprocessors,memoriesandperipherals becamesmallerandfaster.Forexample,the?rstcommercialcomputerUNIVACIcosted $1 million dollars, occupied 943 cubic feet space and could perform 1,905 operations per second [94]. Now, a processor present in an electric shaver easily outperforms the early mainframe computers. The miniaturization is largely due to the efforts of engineers and scientists that made the expeditious progress in the microelectronic technologies possible. According to Moore’s Law [90], the advances in technology allow us to double the number of transistors on a single silicon chip every 18 months. This has lead to an exponential increase in the number of transistors on a chip, from 2,300 in an Intel 4004 to 42 millions in Intel Itanium processor [55]. Moore’s Law has withstood for 40 years and is predicted to remain valid for at least another decade [91]. Notonlytheminiaturizationanddramaticperformanceimprovementbutalsothesign- icantdropinthepriceofprocessors,hasleadtosituationwheretheyarebeingintegratedinto products, such as cars, televisions and phones which are not usually associated with c- puters.This new trend has also been called the disappearing computer, where the computer does not actually disappear but it is everywhere [85]. Digital devices containing processors now constitute a major part of our daily lives. Asmalllistofsuchdevicesincludesmicrowaveovens,televisionsets,mobilephones,digital cameras, MP3 players and cars. Whenever a system comprises of information processingdigitaldevicestocontrolortoaugmentitsfunctionality,suchasystemistermedanembedded system. Therefore, all the above listed devices can be also classi?ed as embedded systems.

Fast, Efficient and Predictable Memory Accesses presents techniques for designing fast, energy-efficient and timing predictable memory systems. By using a careful combination of compiler optimizations and architectural improvements, we can achieve more than what would be feasible at one of the levels in isolation. The described optimization algorithms achieve the goals of high performance and low energy consumption. In addition to these benefits, the use of scratchpad memories significantly improves the timing predictability of the entire system, leading to tighter worst case execution time bounds (WCET). The WCET is a relevant design parameter for all timing critical systems. In addition, the book covers algorithms to exploit the power down modes of main memories in SDRAM technology, as well as the execute-in-place feature of Flash memories. The final chapter considers the impact of the register file, which is also part of the memory hierarchy.

It is well known that embedded systems have to be implemented efficiently. This requires that processors optimized for certain application domains are used in embedded systems. Such an optimization requires a careful exploration of the design space, including a detailed study of cost/performance tradeoffs. In order to avoid time-consuming assembly language programming during design space exploration, compilers are needed. In order to analyze the effect of various software or hardware configurations on the performance, retargetable compilers are needed that can generate code for numerous different potential hardware configurations. This book provides a comprehensive and up-to-date overview of the fast developing area of retargetable compilers for embedded systems. It describes a large set important tools as well as applications of retargetable compilers at different levels in the design flow. Retargetable Compiler Technology for Embedded Systems is mostly self-contained and requires only fundamental knowledge in software and compiler design. It is intended to be a key reference for researchers and designers working on software, compilers, and processor optimization for embedded systems.

Many of the modern applications of microelectronics require hugeamounts of computations. Despite all recent improvements in fabrication technologies, some of these computations have to be performed in hardware in order to meet deadlines. However, controlling computations by software is frequently pre­ ferred due to the larger flexibility. Hence, in general, modern applications re­ quire a mix of software-based and hardware-based computations. Applications using this mix can be designed with the help of hardware/software co-design systems. Many such co-design systems have been described so far (references can be found in this book), but many of these are based on heuristics. In this book, Niemann describes a co-design system which is based on sound modeling techniques. This system has the following salient features: • Precise cost and performance figures Design decisions for implementing a certain function in hardware or software are based on 'cost and performance figures for the different design alterna­ tives. Hence, good designs can only be expected if these figures are accurate. In order to achieve excellent accuracy, Niemann takes a new approach: the cost of software implementations is derived from the data available about the target processors and from knowledge about the code size. the performance of software implement at ions is computed by compiling the given function and then using static analysis for computing worst case execution times. the cost of hardware implementation is estimated by running higher-Ievel synthesis tools. the performance of hardware implementations is again computed by us­ ing static analysis.