Riko Radojcic

Big things often have small beginnings. As National Security Adviser to the President of the United States, Jane Stewart shepherds an act through congress to subsidize manufacturing of silicon chips on American soil. Argon Zhi, an executive at one of the world's best semiconductor foundries, accepts the responsibility to craft a plan for ensuring the competitiveness of Taiwan's technology companies and ensure the continued independence of his country. Cedric Dyson's job as a Failure Analysis engineer is to figure out why some chips do not work the way they are supposed to. When he notices a pattern among the failing chips sent to his FA lab, he uncovers a shocking truth. Jane, Argon and Cedric, each operating within their professional domains, make a series of decisions that lead to an international blame game which could escalate into an open conflict between the world's powers. Will a new silicon chip factory subsidized by the US government, an act of sabotage compromising a multi-billion dollar fab, and a Failure Analysis expert on the case lead the world to a brink of WWIII?

Achieving cost-effective performance over time requires an organized, disciplined, and time-phased approach to product design, development, qualification, manufacture, and in-service management. Guidebook for Managing Silicon Chip Reliability examines the principal failure mechanisms associated with modern integrated circuits and describes common practices used to resolve them.This quick reference on semiconductor reliability addresses the key question: How will the understanding of failure mechanisms affect the future?Chapters discuss:failure sites, operational loads, and failure mechanism intrinsic device sensitivities electromigration hot carrier aging time dependent dielectric breakdown mechanical stress induced migration alpha particle sensitivity electrostatic discharge (ESD) and electrical overstress latch-up qualification screening guidelines for designing reliabilityGuidebook for Managing Silicon Chip Reliability focuses on device failure and causes throughout - providing a thorough framework on how to model the mechanism, test for defects, and avoid and manage damage. It will serve as an exceptional resource for electrical engineers as well as mechanical engineers working in the field of electronic packaging.

This book presents the real challenges and experiences of managing an advanced semiconductor technology development and integration program – but using a novelized form. The material is presented in a conversational format through a story that follows a fictional narrator as she grows from an intern to a manager in a (fictional) chip company. The story describes the technology development program from management, engineering and human perspectives, and exposes not only the management and technical issues but also the typical work-life balance challenges experienced by engineers working in the technology industry. Use of a series of realistic and representative vignettes, supported by a set of illustrative cartoon-ish panels, presents the serious management topics in a light and readable way.

This book presents a realistic and a holistic review of the microelectronic and semiconductor technology options in the post Moore’s Law regime. Technical tradeoffs, from architecture down to manufacturing processes, associated with the 2.5D and 3D integration technologies, as well as the business and product management considerations encountered when faced by disruptive technology options, are presented. Coverage includes a discussion of Integrated Device Manufacturer (IDM) vs Fabless, vs Foundry, and Outsourced Assembly and Test (OSAT) barriers to implementation of disruptive technology options. This book is a must-read for any IC product team that is considering getting off the Moore’s Law track, and leveraging some of the More-than-Moore technology options for their next microelectronic product.

This book presents a realistic and a holistic review of the microelectronic and semiconductor technology options in the post Moore’s Law regime. Technical tradeoffs, from architecture down to manufacturing processes, associated with the 2.5D and 3D integration technologies, as well as the business and product management considerations encountered when faced by disruptive technology options, are presented. Coverage includes a discussion of Integrated Device Manufacturer (IDM) vs Fabless, vs Foundry, and Outsourced Assembly and Test (OSAT) barriers to implementation of disruptive technology options. This book is a must-read for any IC product team that is considering getting off the Moore’s Law track, and leveraging some of the More-than-Moore technology options for their next microelectronic product.

This book presents the real challenges and experiences of managing an advanced semiconductor technology development and integration program – but using a novelized form. The material is presented in a conversational format through a story that follows a fictional narrator as she grows from an intern to a manager in a (fictional) chip company. The story describes the technology development program from management, engineering and human perspectives, and exposes not only the management and technical issues but also the typical work-life balance challenges experienced by engineers working in the technology industry. Use of a series of realistic and representative vignettes, supported by a set of illustrative cartoon-ish panels, presents the serious management topics in a light and readable way.

Achieving cost-effective performance over time requires an organized, disciplined, and time-phased approach to product design, development, qualification, manufacture, and in-service management. Guidebook for Managing Silicon Chip Reliability examines the principal failure mechanisms associated with modern integrated circuits and describes common practices used to resolve them.This quick reference on semiconductor reliability addresses the key question: How will the understanding of failure mechanisms affect the future?Chapters discuss:failure sites, operational loads, and failure mechanism intrinsic device sensitivities electromigration hot carrier aging time dependent dielectric breakdown mechanical stress induced migration alpha particle sensitivity electrostatic discharge (ESD) and electrical overstress latch-up qualification screening guidelines for designing reliabilityGuidebook for Managing Silicon Chip Reliability focuses on device failure and causes throughout - providing a thorough framework on how to model the mechanism, test for defects, and avoid and manage damage. It will serve as an exceptional resource for electrical engineers as well as mechanical engineers working in the field of electronic packaging.