Rolf Drechsler

This book introduces several novel approaches to pave the way for the next generation of integrated circuits, which can be successfully and reliably integrated, even in safety-critical applications. The authors describe new measures to address the rising challenges in the field of design for testability, debug, and reliability, as strictly required for state-of-the-art circuit designs. In particular, this book combines formal techniques, such as the Satisfiability (SAT) problem and the Bounded Model Checking (BMC), to address the arising challenges concerning the increase in test data volume, as well as test application time and the required reliability. All methods are discussed in detail and evaluated extensively, while considering industry-relevant benchmark candidates. All measures have been integrated into a common framework, which implements standardized software/hardware interfaces.

Können wir uns heute noch ein Leben ohne Computer vorstellen? Wie würde unser Tagesablauf ohne Smartphone aussehen? An welchen Stellen hilft uns Technologie, an welchen macht sie das Leben komplizierter? Welche Entwicklungen zeichnen sich ab, welche Auswirkungen werden diese haben? Das alles und mehr steht im Zentrum des Lebens von Nœrdman, dem Nerd aus dem Norden. In humorvoller und informativer Weise werden Themen des Alltags aufgegriffen, erläutert und ein Blick in die Zukunft gewagt. Denn irgendwie sind wir ja alle zu Nerds geworden. Gehörst Du zu den „digital natives“, die in die moderne Computerwelt hineingeboren wurden, oder möchtest zumindest mit diesen reden können? Das Buch richtet sich an Menschen aller Altersgruppen deren Privat- und Arbeitswelt durch die Digitalisierung massiv verändert wurde.

This book presents a comprehensive set of techniques that enhance all key aspects of a modern Virtual Prototype (VP)-based design flow. The authors emphasize automated formal verification methods, as well as advanced coverage-guided analysis and testing techniques, tailored for SystemC-based VPs and also the associated Software (SW). Coverage also includes VP modeling techniques that handle functional as well as non-functional aspects and also describes correspondence analyses between the Hardware- and VP-level to utilize information available at different levels of abstraction. All approaches are discussed in detail and are evaluated extensively, using several experiments to demonstrate their effectiveness in enhancing the VP-based design flow. Furthermore, the book puts a particular focus on the modern RISC-V ISA, with several case-studies covering modeling as well as VP and SW verification aspects.

This book describes a comprehensive approach for synthesis and optimization of logic-in-memory computing hardware and architectures using memristive devices, which creates a firm foundation for practical applications. Readers will get familiar with a new generation of computer architectures that potentially can perform faster, as the necessity for communication between the processor and memory is surpassed. The discussion includes various synthesis methodologies and optimization algorithms targeting implementation cost metrics including latency and area overhead as well as the reliability issue caused by short memory lifetime.Presents a comprehensive synthesis flow for the emerging field of logic-in-memory computing;Describes automated compilation of programmable logic-in-memory computer architectures;Includes several effective optimization algorithm also applicable to classical logic synthesis;Investigates unbalanced write traffic in logic-in-memory architectures and describes wear leveling approaches to alleviate it.

This book describes a set of SystemC-based virtual prototype analysis methodologies, including design understanding, verification, security validation, and design space exploration. Readers will gain an overview of the latest research results in the field of Electronic Design Automation (EDA) at the Electronic System Level (ESL). The methodologies discussed enable readers to tackle easily key tasks and applications in the design process.

This book provides a comprehensive discussion of UML/OCL methods and design flow, for automatic validation and verification of hardware and software systems. While the presented flow focuses on using satisfiability solvers, the authors also describe how these methods can be used for any other automatic reasoning engine. Additionally, the design flow described is applied to a broad variety of validation and verification tasks. The authors also cover briefly how non-functional properties such as timing constraints can be handled with the described flow.

This book describes a comprehensive approach for synthesis and optimization of logic-in-memory computing hardware and architectures using memristive devices, which creates a firm foundation for practical applications. Readers will get familiar with a new generation of computer architectures that potentially can perform faster, as the necessity for communication between the processor and memory is surpassed. The discussion includes various synthesis methodologies and optimization algorithms targeting implementation cost metrics including latency and area overhead as well as the reliability issue caused by short memory lifetime.Presents a comprehensive synthesis flow for the emerging field of logic-in-memory computing;Describes automated compilation of programmable logic-in-memory computer architectures;Includes several effective optimization algorithm also applicable to classical logic synthesis;Investigates unbalanced write traffic in logic-in-memory architectures and describes wear leveling approaches to alleviate it.

This book describes reliable and efficient design automation techniques for the design and implementation of an approximate computing system. The authors address the important facets of approximate computing hardware design - from formal verification and error guarantees to synthesis and test of approximation systems. They provide algorithms and methodologies based on classical formal verification, synthesis and test techniques for an approximate computing IC design flow. This is one of the first books in Approximate Computing that addresses the design automation aspects, aiming for not only sketching the possibility, but providing a comprehensive overview of different tasks and especially how they can be implemented.

This book presents exact, that is minimal, solutions to individual steps in the design process for Digital Microfluidic Biochips (DMFBs), as well as a one-pass approach that combines all these steps in a single process. All of the approaches discussed are based on a formal model that can easily be extended to cope with further design problems. In addition to the exact methods, heuristic approaches are provided and the complexity classes of various design problems are determined.Presents exact methods to tackle a variety of design problems for Digital Microfluidic Biochips (DMFBs);Describes an holistic, one-pass approach solving different design steps all at once;Based on a formal model of DMFBs that is easily adaptable to deal with further design tasks.

This book describes reliable and efficient design automation techniques for the design and implementation of an approximate computing system. The authors address the important facets of approximate computing hardware design - from formal verification and error guarantees to synthesis and test of approximation systems. They provide algorithms and methodologies based on classical formal verification, synthesis and test techniques for an approximate computing IC design flow. This is one of the first books in Approximate Computing that addresses the design automation aspects, aiming for not only sketching the possibility, but providing a comprehensive overview of different tasks and especially how they can be implemented.

This book presents exact, that is minimal, solutions to individual steps in the design process for Digital Microfluidic Biochips (DMFBs), as well as a one-pass approach that combines all these steps in a single process. All of the approaches discussed are based on a formal model that can easily be extended to cope with further design problems. In addition to the exact methods, heuristic approaches are provided and the complexity classes of various design problems are determined.Presents exact methods to tackle a variety of design problems for Digital Microfluidic Biochips (DMFBs);Describes an holistic, one-pass approach solving different design steps all at once;Based on a formal model of DMFBs that is easily adaptable to deal with further design tasks.

This book presents a new optimization flow for quantum circuits realization. At the reversible level, optimization algorithms are presented to reduce the quantum cost. Then, new mapping approaches to decompose reversible circuits to quantum circuits using different quantum libraries are described. Finally, optimization techniques to reduce the quantum cost or the delay are applied to the resulting quantum circuits. Furthermore, this book studies the complexity of reversible circuits and quantum circuits from a theoretical perspective.

This book provides a comprehensive discussion of UML/OCL methods and design flow, for automatic validation and verification of hardware and software systems. While the presented flow focuses on using satisfiability solvers, the authors also describe how these methods can be used for any other automatic reasoning engine. Additionally, the design flow described is applied to a broad variety of validation and verification tasks. The authors also cover briefly how non-functional properties such as timing constraints can be handled with the described flow.

Computer umgeben uns heute in fast allen Lebensbereichen. Sie erleichtern uns nicht nur als PC oder Laptop die Arbeit, sondern sind auch eingebettet in zahlreiche Objekte unseres täglichen Lebens – vom Auto bis zur Waschmaschine. Doch wie funktionieren moderne Rechner eigentlich? Und wie werden diese hochkomplexen, aus Milliarden Komponenten bestehenden Geräte entworfen?Das Buch erklärt auf verständliche, informative und unterhaltsame Weise den Aufbau und die Funktionsweise heutiger Computersysteme. Einzelne inhaltliche Abschnitte werden durch Links zu Videos ergänzt, in denen Professor Rolf Drechsler relevante Themen prägnant und pointiert vorstellt.

This book introduces a new level of abstraction that closes the gap between the textual specification of embedded systems and the executable model at the Electronic System Level (ESL). Readers will be enabled to operate at this new, Formal Specification Level (FSL), using models which not only allow significant verification tasks in this early stage of the design flow, but also can be extracted semi-automatically from the textual specification in an interactive manner. The authors explain how to use these verification tasks to check conceptual properties, e.g. whether requirements are in conflict, as well as dynamic behavior, in terms of execution traces.

This book provides a comprehensive overview of automatic model refinement, which helps readers close the gap between initial textual specification and its desired implementation. The authors enable readers to follow two “directions” for refinement: Vertical refinement, for adding detail and precision to single description for a given model and Horizontal refinement, which considers several views on one level of abstraction, refining the system specification by dedicated descriptions for structure or behavior. The discussion includes several methods which support designers of electronic systems in this refinement process, including verification methods to check automatically whether a refinement has been conducted as intended.

This book presents a new optimization flow for quantum circuits realization. At the reversible level, optimization algorithms are presented to reduce the quantum cost. Then, new mapping approaches to decompose reversible circuits to quantum circuits using different quantum libraries are described. Finally, optimization techniques to reduce the quantum cost or the delay are applied to the resulting quantum circuits. Furthermore, this book studies the complexity of reversible circuits and quantum circuits from a theoretical perspective.

This book introduces a new level of abstraction that closes the gap between the textual specification of embedded systems and the executable model at the Electronic System Level (ESL). Readers will be enabled to operate at this new, Formal Specification Level (FSL), using models which not only allow significant verification tasks in this early stage of the design flow, but also can be extracted semi-automatically from the textual specification in an interactive manner. The authors explain how to use these verification tasks to check conceptual properties, e.g. whether requirements are in conflict, as well as dynamic behavior, in terms of execution traces.

Debugging becomes more and more the bottleneck to chip design productivity, especially while developing modern complex integrated circuits and systems at the Electronic System Level (ESL). Today, debugging is still an unsystematic and lengthy process. Here, a simple reporting of a failure is not enough, anymore. Rather, it becomes more and more important not only to find many errors early during development but also to provide efficient methods for their isolation. In Debugging at the Electronic System Level the state-of-the-art of modeling and verification of ESL designs is reviewed. There, a particular focus is taken onto SystemC. Then, a reasoning hierarchy is introduced. The hierarchy combines well-known debugging techniques with whole new techniques to improve the verification efficiency at ESL. The proposed systematic debugging approach is supported amongst others by static code analysis, debug patterns, dynamic program slicing, design visualization, property generation, and automatic failure isolation. All techniques were empirically evaluated using real-world industrial designs. Summarized, the introduced approach enables a systematic search for errors in ESL designs. Here, the debugging techniques improve and accelerate error detection, observation, and isolation as well as design understanding.

This book provides an overview of automatic test pattern generation (ATPG) and introduces novel techniques to complement classical ATPG, based on Boolean Satisfiability (SAT). A fast and highly fault efficient SAT-based ATPG framework is presented which is also able to generate high-quality delay tests such as robust path delay tests, as well as tests with long propagation paths to detect small delay defects. The aim of the techniques and methodologies presented in this book is to improve SAT-based ATPG, in order to make it applicable in industrial practice. Readers will learn to improve the performance and robustness of the overall test generation process, so that the ATPG algorithm reliably will generate test patterns for most targeted faults in acceptable run time to meet the high fault coverage demands of industry. The techniques and improvements presented in this book provide the following advantages: Provides a comprehensive introduction to test generation and Boolean Satisfiability (SAT); Describes a highly fault efficient SAT-based ATPG framework; Introduces circuit-oriented SAT solving techniques, which make use of structural information and are able to accelerate the search process significantly;Provides SAT formulations for the prevalent delay faults models, in addition to the classical stuck-at fault model;Includes an industrial perspective on the state-of-the-art in the testing, along with SAT; two topics typically distinguished from each other.