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Kirjailija

Saurabh Chaudhury

Kirjat ja teokset yhdessä paikassa: 2 kirjaa, julkaisuja vuosilta 2013-2019, suosituimpien joukossa Genetic Algorithms for Low Power Logic Optimization and Synthesis. Vertaile teosten hintoja ja tarkista saatavuus suomalaisista kirjakaupoista.

2 kirjaa

Kirjojen julkaisuhaarukka 2013-2019.

Design & Implementation of Low Power & Area Optimized DCTQ Processor

Design & Implementation of Low Power & Area Optimized DCTQ Processor

Debashish Dash; Saurabh Chaudhury

LAP Lambert Academic Publishing
2019
pokkari
Image compression is an important topic in commercial, industrial, and academic applications. Whether it is in commercial photography, industrial imaging, or video, digital pixel information can comprise considerably large amounts of data. Management of such data can involve significant overhead in computational complexity, storage, and data processing. Typical access speeds for storage mediums are inversely proportional to capacity.Through data compression, such tasks can be optimized. In this book authors have reviewed the state-of-art optimization techniques that are being implemented in designing DCT based Processor for image compression, tailored some of them and also incorporated new ideas to further optimize the design.
Genetic Algorithms for Low Power Logic Optimization and Synthesis
This book aims at digital logic optimization and synthesis issues from the aspects of low power, area and testability. The issue of logic optimization which is essentially a technology-independent optimization has been addressed in different chapters are based on the research problems, which include, two-level logics, multi-level logics, AND-OR/XOR based logics, BDDs, and Finite State Machines synthesis. Genetic Algorithms have been extensively used to frame the problems and to derive the best solution of it. The topics presented in each of the chapters from 3-7 are based on the research carried out in each of the areas mentioned earlier. I am sure that the book will be quite useful to readers interested in logic minimization and to researchers who are interested in doing research in the area of low power VLSI and like to carry out further work in the field of logic optimization and synthesis.