Nishant Kumar

Este livro prop e o design e a arquitetura de um processador pipeline dual-core dinamicamente escal vel. A metodologia do design a fus o central de dois processadores, onde dois n cleos independentes podem se transformar dinamicamente em uma unidade de processamento maior, ou podem ser usados como elementos de processamento distintos para alcan ar alto desempenho sequencial e alto desempenho paralelo. O processador oferece dois modos de execu o. O modo 1 o modo multiprogramming para execu o de fluxos de instru es de largura de dados inferior, ou seja, cada n cleo pode realizar opera es de 16 bits individualmente. O desempenho melhorado neste modo devido execu o paralela de instru es em ambos os n cleos, ao custo da rea. No modo 2, ambos os n cleos de processamento s o acoplados e comportam-se como uma nica unidade de processamento de alta largura de dados, ou seja, podem realizar opera es de 32 bits. necess ria comunica o adicional entre n cleos para implementar este modo. O modo pode mudar dinamicamente; portanto, este processador pode fornecer multifuncionalidade com um nico design. O design e a verifica o do processador foram realizados com sucesso usando Verilog na plataforma Xilinx 14.1. O processador verificado tanto em simula o quanto em s ntese com a ajuda de programas de teste.

Książka ta przedstawia projekt i architekturę dynamicznie skalowalnego dwurdzeniowego procesora rurociągowego. Metodologia projektu polega na polączeniu dw ch procesor w, w kt rym dwa niezależne rdzenie mogą dynamicznie przeksztalcac się w większą jednostkę przetwarzającą lub mogą byc wykorzystywane jako odrębne elementy przetwarzające w celu osiągnięcia wysokiej wydajności sekwencyjnej i wysokiej wydajności r wnoleglej. Procesor oferuje dwa tryby dzialania. Tryb 1 to tryb wielozadaniowy do wykonywania strumieni instrukcji o mniejszej szerokości danych, tzn. każdy rdzeń może wykonywac operacje 16-bitowe indywidualnie. Wydajnośc w tym trybie jest lepsza dzięki r wnoleglemu wykonywaniu instrukcji w obu rdzeniach, ale kosztem powierzchni. W trybie 2 oba rdzenie przetwarzające są polączone i dzialają jak jedna jednostka przetwarzająca o dużej szerokości danych, tzn. mogą wykonywac operacje 32-bitowe. Aby zrealizowac ten tryb, konieczna jest dodatkowa komunikacja między rdzeniami. Tryb ten może się dynamicznie zmieniac, dzięki czemu procesor ten może zapewnic wielofunkcyjnośc przy użyciu jednej konstrukcji. Projektowanie i weryfikacja procesora zostaly pomyślnie przeprowadzone przy użyciu języka Verilog na platformie Xilinx 14.1. Procesor zostal zweryfikowany zar wno w symulacji, jak i syntezie przy pomocy program w testowych.

Questo libro propone la progettazione e l'architettura di un processore dual-core in pipeline dinamicamente scalabile. La metodologia di progettazione consiste nella fusione dei due processori, in cui due core indipendenti possono trasformarsi dinamicamente in un'unit di elaborazione pi grande, oppure possono essere utilizzati come elementi di elaborazione distinti per ottenere elevate prestazioni sequenziali e parallele. Il processore offre due modalit di esecuzione. La modalit 1 una modalit multiprogrammazione per l'esecuzione di flussi di istruzioni con larghezza di dati inferiore, ovvero ogni core pu eseguire operazioni a 16 bit individualmente. In questa modalit le prestazioni sono migliorate grazie all'esecuzione parallela delle istruzioni in entrambi i core, a scapito dell'area. Nella modalit 2, entrambi i core di elaborazione sono accoppiati e si comportano come un'unica unit di elaborazione con larghezza di dati elevata, ovvero possono eseguire operazioni a 32 bit. Per realizzare questa modalit necessaria una comunicazione aggiuntiva tra i core. La modalit pu cambiare dinamicamente; pertanto, questo processore pu fornire multifunzionalit con un unico design. La progettazione e la verifica del processore sono state eseguite con successo utilizzando Verilog sulla piattaforma Xilinx 14.1. Il processore stato verificato sia in simulazione che in sintesi con l'aiuto di programmi di test.

Cet ouvrage propose la conception et l'architecture d'un processeur double coeur en pipeline volutivit dynamique. La m thodologie de conception repose sur la fusion des coeurs de deux processeurs, o deux coeurs ind pendants peuvent se transformer dynamiquement en une unit de traitement plus grande, ou tre utilis s comme l ments de traitement distincts pour atteindre des performances s quentielles et parall les lev es. Le processeur offre deux modes d'ex cution. Le mode 1 est un mode multiprogrammation pour l'ex cution de flux d'instructions de faible largeur de donn es, c'est- -dire que chaque coeur peut effectuer des op rations 16 bits individuellement. Les performances sont am lior es dans ce mode gr ce l'ex cution parall le des instructions dans les deux coeurs, au d triment de l'espace. Dans le mode 2, les deux coeurs de traitement sont coupl s et se comportent comme une seule unit de traitement largeur de donn es lev e, c'est- -dire qu'ils peuvent effectuer des op rations 32 bits. Une communication suppl mentaire entre les coeurs est n cessaire pour mettre en oeuvre ce mode. Le mode peut changer de mani re dynamique; ce processeur peut donc offrir plusieurs fonctions avec une conception unique. La conception et la v rification du processeur ont t r alis es avec succ s l'aide de Verilog sur la plateforme Xilinx 14.1. Le processeur a t v rifi la fois en simulation et en synth se l'aide de programmes de test.

Dieses Buch schl gt den Entwurf und die Architektur eines dynamisch skalierbaren Dual-Core-Pipeline-Prozessors vor. Die Methodik des Entwurfs besteht in der Kernfusion zweier Prozessoren, wobei zwei unabh ngige Kerne dynamisch zu einer gr eren Verarbeitungseinheit umgewandelt werden k nnen oder als separate Verarbeitungselemente verwendet werden k nnen, um eine hohe sequentielle Leistung und eine hohe parallele Leistung zu erzielen. Der Prozessor bietet zwei Ausf hrungsmodi. Modus 1 ist der Multiprogrammierungsmodus f r die Ausf hrung von Befehlsstr men mit geringerer Datenbreite, d. h. jeder Kern kann einzeln 16-Bit-Operationen ausf hren. In diesem Modus wird die Leistung durch die parallele Ausf hrung von Befehlen in beiden Kernen auf Kosten der Fl che verbessert. In Modus 2 sind beide Prozessorkerne gekoppelt und verhalten sich wie eine einzige Verarbeitungseinheit mit hoher Datenbreite, d. h. sie k nnen 32-Bit-Operationen ausf hren. Um diesen Modus zu realisieren, ist eine zus tzliche Kommunikation zwischen den Kernen erforderlich. Der Modus kann dynamisch umgeschaltet werden, sodass dieser Prozessor mit einem einzigen Design mehrere Funktionen bieten kann. Das Design und die Verifizierung des Prozessors wurden erfolgreich mit Verilog auf der Xilinx 14.1-Plattform durchgef hrt. Der Prozessor wurde sowohl in der Simulation als auch in der Synthese mit Hilfe von Testprogrammen verifiziert.

This book analyzes the role of laws and the judiciary in the process of censorship in India. It examines the rationales and observations produced by the judiciary when demands for censorship are directed against publications that allegedly offend religious sentiments. Focusing on a micro-level analysis of censorship of publications, it presents a hard case to understand the limitations of freedom of expression and the role played by the judiciary in defining its boundaries. The volume traces the evolution of laws governing freedom of expression since the colonial period and the context in which these laws were amended after Independence. It also explicates how the legal process – the structural and functional aspects of working of judiciary – affects the fate of freedom of expression in India. Employing comparative legal analysis, it tries to understand and situate the Indian case within the larger discourse of censorship and freedom of expression around the world, thereby marking its similarities and differences. In unravelling the politics of censorship, the author also examines the interaction among different stakeholders like government, non-state actors and the judiciary.A tract for our times, this book will be of great interest to scholars and researchers of law, especially constitutional law and fundamental rights, politics, especially political theory and Indian politics, modern India and South Asian studies.

This book analyzes the role of laws and the judiciary in the process of censorship in India. It examines the rationales and observations produced by the judiciary when demands for censorship are directed against publications that allegedly offend religious sentiments. Focusing on a micro-level analysis of censorship of publications, it presents a hard case to understand the limitations of freedom of expression and the role played by the judiciary in defining its boundaries. The volume traces the evolution of laws governing freedom of expression since the colonial period and the context in which these laws were amended after Independence. It also explicates how the legal process – the structural and functional aspects of working of judiciary – affects the fate of freedom of expression in India. Employing comparative legal analysis, it tries to understand and situate the Indian case within the larger discourse of censorship and freedom of expression around the world, thereby marking its similarities and differences. In unravelling the politics of censorship, the author also examines the interaction among different stakeholders like government, non-state actors and the judiciary.A tract for our times, this book will be of great interest to scholars and researchers of law, especially constitutional law and fundamental rights, politics, especially political theory and Indian politics, modern India and South Asian studies.