Rolf Drechsler

A quality-driven design and verification flow for digital systems is developed and presented in Quality-Driven SystemC Design. Two major enhancements characterize the new flow: First, dedicated verification techniques are integrated which target the different levels of abstraction. Second, each verification technique is complemented by an approach to measure the achieved verification quality. The new flow distinguishes three levels of abstraction (namely system level, top level and block level) and can be incorporated in existing approaches. After reviewing the preliminary concepts, in the following chapters the three levels for modeling and verification are considered in detail. At each level the verification quality is measured. In summary, following the new design and verification flow a high overall quality results.

A quality-driven design and verification flow for digital systems is developed and presented in Quality-Driven SystemC Design. Two major enhancements characterize the new flow: First, dedicated verification techniques are integrated which target the different levels of abstraction. Second, each verification technique is complemented by an approach to measure the achieved verification quality. The new flow distinguishes three levels of abstraction (namely system level, top level and block level) and can be incorporated in existing approaches. After reviewing the preliminary concepts, in the following chapters the three levels for modeling and verification are considered in detail. At each level the verification quality is measured. In summary, following the new design and verification flow a high overall quality results.

In Test Pattern Generation using Boolean Proof Engines, we give an introduction to ATPG. The basic concept and classical ATPG algorithms are reviewed. Then, the formulation as a SAT problem is considered. As the underlying engine, modern SAT solvers and their use on circuit related problems are comprehensively discussed. Advanced techniques for SAT-based ATPG are introduced and evaluated in the context of an industrial environment. The chapters of the book cover efficient instance generation, encoding of multiple-valued logic, usage of various fault models, and detailed experiments on multi-million gate designs. The book describes the state of the art in the field, highlights research aspects, and shows directions for future work.

This book deals with formal and practical approaches for early fast modeling and verification of complex digital processor hardware and software using SystemC-based virtual prototypes. As a special focus, modeling approaches of instruction-level behavior of System-on-Chips and the connected off-chip digital devices are addressed. Featured verification approaches are based on symbolic execution of simulated hardware devices or on classical discrete execution of the whole system with dynamic data flow tracking. The approaches are accompanied by Case-Studies that develop and build on top of an open-source RISC-V SoC simulation.In Particular, this book:

In recent years, significant effort has been put into developing formal verification approaches in both academic and industrial research. In practice, these techniques often give satisfying results for some types of circuits, while they fail for others. A major challenge in this domain is that the verification techniques suffer from unpredictability in their performance. The only way to overcome this challenge is the calculation of bounds for the space and time complexities. If a verification method has polynomial space and time complexities, scalability can be guaranteed. In this monograph, Polynomial Formal Verification (PFV) of arithmetic circuits is evaluated. The importance and advantages of PFV are discussed, and subsequently it is proved that PFV of different types of arithmetic circuits, including adders, multipliers, and Arithmetic Logic Units (ALUs), is possible. Furthermore, the exact upper-bound space and time complexities of verifying these circuits are calculated.

Dieses Buch beschreibt eine umfassende Kombination von Methoden, die den modernen Virtual Prototype (VP)-basierten Verifikationsfluss für heterogene Systems-on-Chip (SOCs) stark verbessern. Insbesondere kombiniert das Buch Verifikations- und Analyseaspekte über verschiedene Stufen des VP-basierten Verifikationsflusses hinweg und bietet eine neue Perspektive auf die Verifikation, indem es fortschrittliche Techniken wie metamorphes Testen, Datenfluss-Testen und Informationsfluss-Testen einsetzt. Darüber hinaus legt das Buch einen starken Schwerpunkt auf fortschrittliche, abdeckungsorientierte Methoden zur Verifizierung des funktionalen Verhaltens des SOC sowie zur Gewährleistung seiner Sicherheit.Bietet eine umfassende Einführung in den modernen VP-basierten Verifikationsablauf für heterogene SOCs;Stellt eine neuartige metamorphe Testtechnik für heterogene SOCs vor, die keine Referenzmodelle erfordert;Enthält automatisierte, fortschrittliche, auf Datenflussabdeckung basierende Methoden, die auf SystemC/AMS-basierte VP zugeschnitten sind;Beschreibt erweiterte funktionale abdeckungsgesteuerte Methoden zur Verifizierung verschiedener funktionaler Verhaltensweisen von RF-Verstärkern.

This book deals with formal and practical approaches for early fast modeling and verification of complex digital processor hardware and software using SystemC-based virtual prototypes. As a special focus, modeling approaches of instruction-level behavior of System-on-Chips and the connected off-chip digital devices are addressed. Featured verification approaches are based on symbolic execution of simulated hardware devices or on classical discrete execution of the whole system with dynamic data flow tracking. The approaches are accompanied by Case-Studies that develop and build on top of an open-source RISC-V SoC simulation.In Particular, this book:

This book addresses the challenging tasks of verifying and debugging structurally complex multipliers. In the area of verification, the authors first investigate the challenges of Symbolic Computer Algebra (SCA)-based verification, when it comes to proving the correctness of multipliers. They then describe three techniques to improve and extend SCA: vanishing monomials removal, reverse engineering, and dynamic backward rewriting. This enables readers to verify a wide variety of multipliers, including highly complex and optimized industrial benchmarks. The authors also describe a complete debugging flow, including bug localization and fixing, to find the location of bugs in structurally complex multipliers and make corrections.

In diesem Buch werden mehrere neue Ansätze vorgestellt, die den Weg für die nächste Generation integrierter Schaltungen ebnen, die auch in sicherheitskritischen Anwendungen erfolgreich und zuverlässig integriert werden können. Die Autoren beschreiben neue Maßnahmen zur Bewältigung der steigenden Herausforderungen im Bereich des Designs für Testbarkeit, Fehlersuche und Zuverlässigkeit, die für moderne Schaltungsentwürfe unbedingt erforderlich sind. Insbesondere werden in diesem Buch formale Techniken wie das Satisfiability (SAT)-Problem und das Bounded Model Checking (BMC) kombiniert, um die entstehenden Herausforderungen in Bezug auf die Zunahme des Testdatenvolumens, die Testanwendungszeit und die erforderliche Zuverlässigkeit zu bewältigen. Alle Methoden werden detailliert diskutiert und unter Berücksichtigung von industrie-relevanten Benchmark-Kandidaten ausführlich evaluiert. Alle Maßnahmen wurden in ein gemeinsames Framework integriert, das standardisierte Software/Hardware-Schnittstellen implementiert.

Dieses Buch beschreibt eine Reihe von SystemC-basierten Analysemethoden für virtuelle Prototypen, einschließlich Entwurfsverständnis, Verifikation, Sicherheitsvalidierung und Entwurfsraumuntersuchung. Der Leser erhält einen Überblick über die neuesten Forschungsergebnisse auf dem Gebiet der Electronic Design Automation (EDA) auf der elektronischen Systemebene (ESL). Die besprochenen Methoden ermöglichen es den Lesern, wichtige Aufgaben und Anwendungen im Entwurfsprozess leicht zu bewältigen.Übersetzt mit www.DeepL.com/Translator (kostenlose Version)

This book describes a comprehensive combination of methodologies that strongly enhance the modern Virtual Prototype (VP)-based verification flow for heterogeneous systems-on-chip (SOCs). In particular, the book combines verification and analysis aspects across various stages of the VP-based verification flow, providing a new perspective on verification by leveraging advanced techniques, like metamorphic testing, data flow testing, and information flow testing. In addition, the book puts a strong emphasis on advanced coverage-driven methodologies to verify the functional behavior of the SOC as well as ensure its security.Provides an extensive introduction to the modern VP-based verification flow for heterogeneous SOCs;Introduces a novel metamorphic testing technique for heterogeneous SOCs which does not require reference models;Includes automated advanced data flow coverage-driven methodologies tailored for SystemC/AMS-based VPs;Describes enhanced functional coverage-driven methodologies to verify various functional behaviors of RF amplifiers.

Dieses Buch beschreibt einen umfassenden Ansatz für die Synthese und Optimierung von Logic-in-Memory-Computing-Hardware und -Architekturen mit memristiven Bauelementen, der eine solide Grundlage für praktische Anwendungen schafft. Die Leser werden mit einer neuen Generation von Computerarchitekturen vertraut gemacht, die potenziell schneller arbeiten können, da die Notwendigkeit der Kommunikation zwischen Prozessor und Speicher überwunden wird. Die Diskussion umfasst verschiedene Synthesemethoden und Optimierungsalgorithmen, die auf Implementierungskostenmetriken wie Latenzzeit und Flächen abzielen, sowie das Problem der Zuverlässigkeit, das durch die kurze Lebensdauer des Speichers verursacht wird. Präsentiert einen umfassenden Synthesefluss für das aufkommende Feld des Logic-in-Memory-Computings; Beschreibt die automatische Kompilierung von programmierbaren Logik-in-Memory-Computerarchitekturen;Enthält mehrere effektive Optimierungsalgorithmen, die auch auf die klassische Logiksynthese anwendbar sind;Untersucht den unausgewogenen Schreibverkehr in Logic-in-Memory-Architekturen und beschreibt Ansätze zum Verschleißausgleich, um diesen zu verringern.

This book addresses the challenging tasks of verifying and debugging structurally complex multipliers. In the area of verification, the authors first investigate the challenges of Symbolic Computer Algebra (SCA)-based verification, when it comes to proving the correctness of multipliers. They then describe three techniques to improve and extend SCA: vanishing monomials removal, reverse engineering, and dynamic backward rewriting. This enables readers to verify a wide variety of multipliers, including highly complex and optimized industrial benchmarks. The authors also describe a complete debugging flow, including bug localization and fixing, to find the location of bugs in structurally complex multipliers and make corrections.

This book discusses the main tasks of Design Automation for Field-coupled Nanocomputing (FCN) technologies, in order to enable large-scale composition of elementary building blocks, that obtain correct systems from given function specifications. To this end, a holistic design flow is described, which covers exact and scalable placement & routing, one-pass logic synthesis, novel clocking mechanisms for data synchronization, and formal verification for obtained circuit layouts. Additionally, theoretical groundwork is presented that lays the foundation for any algorithmic consideration in the future. Furthermore, an open-source FCN design framework called fiction, which contains implementations of all proposed techniques, is presented and made publicly available. The approaches discussed in this book address obstacles that have existed since the conceptualization of the FCN paradigm and could not be resolved since then. As a result, this book substantially advances the state of the artin design automation for FCN technologies.

Dieses Buch stellt eine umfassende Reihe von Techniken vor, die alle wichtigen Aspekte eines modernen Virtual Prototype (VP)-basierten Entwurfsablaufs verbessern. Die Autoren legen den Schwerpunkt auf automatisierte formale Verifikationsmethoden sowie auf fortgeschrittene, abdeckungsgeleitete Analyse- und Testtechniken, die auf SystemC-basierte VP und die zugehörige Software (SW) zugeschnitten sind. Die Abdeckung umfasst auch VP-Modellierungstechniken, die sowohl funktionale als auch nicht-funktionale Aspekte behandeln, und beschreibt zudem Korrespondenzanalysen zwischen der Hardware- und VP-Ebene, um die auf verschiedenen Abstraktionsebenen verfügbaren Informationen zu nutzen. Alle Ansätze werden ausführlich diskutiert und anhand mehrerer Experimente evaluiert, um ihre Effektivität bei der Verbesserung des VP-basierten Entwurfsablaufs zu demonstrieren. Darüber hinaus legt das Buch einen besonderen Schwerpunkt auf den modernen RISC-V ISA, mit mehreren Fallstudien, die sowohl Aspekteder Modellierung als auch der VP- und SW-Verifikation abdecken.

This book describes a comprehensive combination of methodologies that strongly enhance the modern Virtual Prototype (VP)-based verification flow for heterogeneous systems-on-chip (SOCs). In particular, the book combines verification and analysis aspects across various stages of the VP-based verification flow, providing a new perspective on verification by leveraging advanced techniques, like metamorphic testing, data flow testing, and information flow testing. In addition, the book puts a strong emphasis on advanced coverage-driven methodologies to verify the functional behavior of the SOC as well as ensure its security.Provides an extensive introduction to the modern VP-based verification flow for heterogeneous SOCs;Introduces a novel metamorphic testing technique for heterogeneous SOCs which does not require reference models;Includes automated advanced data flow coverage-driven methodologies tailored for SystemC/AMS-based VPs;Describes enhanced functional coverage-driven methodologies to verify various functional behaviors of RF amplifiers.

This book introduces several novel approaches to pave the way for the next generation of integrated circuits, which can be successfully and reliably integrated, even in safety-critical applications. The authors describe new measures to address the rising challenges in the field of design for testability, debug, and reliability, as strictly required for state-of-the-art circuit designs. In particular, this book combines formal techniques, such as the Satisfiability (SAT) problem and the Bounded Model Checking (BMC), to address the arising challenges concerning the increase in test data volume, as well as test application time and the required reliability. All methods are discussed in detail and evaluated extensively, while considering industry-relevant benchmark candidates. All measures have been integrated into a common framework, which implements standardized software/hardware interfaces.

This book discusses the main tasks of Design Automation for Field-coupled Nanocomputing (FCN) technologies, in order to enable large-scale composition of elementary building blocks, that obtain correct systems from given function specifications. To this end, a holistic design flow is described, which covers exact and scalable placement & routing, one-pass logic synthesis, novel clocking mechanisms for data synchronization, and formal verification for obtained circuit layouts. Additionally, theoretical groundwork is presented that lays the foundation for any algorithmic consideration in the future. Furthermore, an open-source FCN design framework called fiction, which contains implementations of all proposed techniques, is presented and made publicly available. The approaches discussed in this book address obstacles that have existed since the conceptualization of the FCN paradigm and could not be resolved since then. As a result, this book substantially advances the state of the artin design automation for FCN technologies.

This book presents a comprehensive set of techniques that enhance all key aspects of a modern Virtual Prototype (VP)-based design flow. The authors emphasize automated formal verification methods, as well as advanced coverage-guided analysis and testing techniques, tailored for SystemC-based VPs and also the associated Software (SW). Coverage also includes VP modeling techniques that handle functional as well as non-functional aspects and also describes correspondence analyses between the Hardware- and VP-level to utilize information available at different levels of abstraction. All approaches are discussed in detail and are evaluated extensively, using several experiments to demonstrate their effectiveness in enhancing the VP-based design flow. Furthermore, the book puts a particular focus on the modern RISC-V ISA, with several case-studies covering modeling as well as VP and SW verification aspects.

This book describes a set of SystemC-based virtual prototype analysis methodologies, including design understanding, verification, security validation, and design space exploration. Readers will gain an overview of the latest research results in the field of Electronic Design Automation (EDA) at the Electronic System Level (ESL). The methodologies discussed enable readers to tackle easily key tasks and applications in the design process.